Carlo Samori

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Gabriele Bè

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Publications

2024
[j56]
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Gabriele Zanoletti, Lorenzo Scaletti, Gabriele Bè, Luca Ricci, Michele Rocco, Luca Bertulessi, Carlo Samori, Andrea Bonfanti:
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1551-1555 (2024)
2023
[c52]
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Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, Luca Bertulessi, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti:
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits 2023: 1-2
2022
[j48]
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Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Lorenzo Scaletti, Mario Mercandelli, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3645-3649 (2022)
[c50]
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Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Luca Bertulessi, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. ISCAS 2022: 900-904
[c48]
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Lorenzo Scaletti, Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Mario Mercandelli, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS 2022: 20-24

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