Yi-Ming Wang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jinn-Shyan Wang

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Publications

2010
[j3]
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Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. IEEE J. Solid State Circuits 45(5): 1036-1047 (2010)
[c12]
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Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A 55nm 1GHz one-cycle-locking de-skewing circuit. ISCAS 2010: 1755-1758
2007
[c8]
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  - conf/isscc/WangCWY07
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Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh:
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. ISSCC 2007: 294-604
2006
[c7]
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  - conf/iscas/WangWCL06
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Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu:
An improved SAR controller for DLL applications. ISCAS 2006
2005
[c6]
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Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang:
An all-digital pulsewidth control loop. ISCAS (2) 2005: 1258-1261
2004
[j1]
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Yi-Ming Wang, Jinn-Shyan Wang:
A low-power half-delay-line fast skew-compensation circuit. IEEE J. Solid State Circuits 39(6): 906-918 (2004)
[c5]
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Yi-Ming Wang, Jinn-Shyan Wang:
A reliable low-power fast skew-compensation circuit. ASP-DAC 2004: 547-548
[c4]
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Yi-Ming Wang, Jinn-Shyan Wang:
An all-digital 50% duty-cycle corrector. ISCAS (2) 2004: 925-928
2000
[c1]
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  - conf/iscas/YangWW00
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Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang:
A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. ISCAS 2000: 665-668

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