David Mahashin

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Sai Lalith Chaitanya Ambatipudi

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Publications

2020
[j1]
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Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE J. Solid State Circuits 55(4): 1086-1095 (2020)
[c5]
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  dblp key:
  - conf/ecoc/RajFCAMHBCGEC20
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  - https://dblp.org/rec/conf/ecoc/RajFCAMHBCGEC20
Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. ECOC 2020: 1-4
2019
[c3]
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  - conf/vlsic/RajFAMHBCGEC19
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Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. VLSI Circuits 2019: 190-
2018
[c2]
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  - conf/vlsic/HudnerCCHNCEPLZ18
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James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits 2018: 47-48

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