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Hwa-Yi Tseng

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2010 – 2019

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2018
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  - conf/aspdac/ChiTLC18
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  - https://dblp.org/rec/conf/aspdac/ChiTLC18
Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Performance-preserved analog routing methodology via wire load reduction. ASP-DAC 2018: 482-487
2017
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Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, Chin Hsia:
Layout placement optimization with isolation rings for high-voltage VLSI circuits. VLSI-DAT 2017: 1-4

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