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ORCIDZhiyuan Liu 0011
Person information
- affiliation: Southeast University, School of Electronic Science and Engineering, National ASIC System Engineering Research Center, Nanjing, China
Other persons with the same name
- Zhiyuan Liu (aka: Zhi-Yuan Liu) — disambiguation page
- Zhiyuan Liu 0001
![[0000-0002-7709-2543]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7709-2543")
— Tsinghua University, Department of Computer Science and Technology, Beijing, China (and 1 more) - Zhiyuan Liu 0002 — Southeast University, Jiangsu, China
- Zhiyuan Liu 0003 — University of Colorado, Boulder, CO, USA
- Zhiyuan Liu 0004 — Chongqing University, China
- Zhiyuan Liu 0005 (aka: Zhi-Yuan Liu 0005) — Harbin Institute of Technology, Automotive Electronic Engineering Center, China (and 1 more)
- Zhiyuan Liu 0006 — Dalian University of Technology, China
- Zhiyuan Liu 0007 — Shandong Normal University, Jinan, China
- Zhiyuan Liu 0008 — Civil Aviation University of China, Tianjin, China
- Zhiyuan Liu 0009 — Beihang University, Beijing, China
- Zhiyuan Liu 0010 — National University of Singapore, Singapore (and 1 more)
- Zhiyuan Liu 0012 — University of North Carolina, UNC, Department of Computer Science, Chapel Hill, USA
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2020 – today
- 2021
[j2]Jingjing Guo, Peng Cao, Mengxiao Li, Yu Gong, Zhiyuan Liu, Geng Bai, Jun Yang:
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 931-944 (2021)- 2020
- [c5]Jingjing Guo, Peng Cao, Mengxiao Li, Zhiyuan Liu, Jun Yang:
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j1]Peng Cao, Zhiyuan Liu, Jingjing Guo, Jiangping Wu:
An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation. IEEE Access 7: 171515-171524 (2019) - [c4]Peng Cao, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. ACM Great Lakes Symposium on VLSI 2019: 323-326 - [c3]Peng Cao, Zhiyuan Liu, Jiangping Wu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Timing Model for Low Voltage Design Considering Process Variation. ICCAD 2019: 1-8 - [c2]Peng Cao, Zhiyuan Liu, Bingqian Xu, Jingjing Guo:
A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time. ICECS 2019: 586-589 - [c1]Peng Cao, Zhiyuan Liu, Jingjing Guo, Haoyu Pang, Jiangping Wu, Jun Yang:
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. NEWCAS 2019: 1-4
Coauthor Index
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