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ORCIDGuoliang Li 0004
Person information
- affiliation: Vastai Technologies, Shanghai, China
- affiliation (former): Advanced Micro Devices Corporation, Shanghai, China
Other persons with the same name
- Guoliang Li (aka: GuoLiang Li, Guo-Liang Li) — disambiguation page
- Guoliang Li 0001
![[0000-0002-1398-0621]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-1398-0621")
— Tsinghua University, Department of Computer Science, TNList, Beijing, China - Guoliang Li 0002 — Huazhong Agricultural University, Wuhan, China (and 2 more)
- Guoliang Li 0003 — Oracle Labs, San Diego, CA, USA (and 2 more)
- Guoliang Li 0005 — Yunnan University, School of Information Science and Engineering, Kunming, China
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2020 – today
- 2021
[j2]Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty:
Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 185-198 (2021)
2010 – 2019
- 2018
- [c7]Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty:
Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism. ITC 2018: 1-10 - [c6]Guoliang Li, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang:
Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures. ITC-Asia 2018: 109-114 - [c5]Zhanwei Zhong, Guoliang Li, Qinfu Yang, Jun Qian, Krishnendu Chakrabarty:
Broadcast-based minimization of the overall access time for the IEEE 1687 network. VTS 2018: 1-6 - 2017
- [j1]Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty:
ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 1030-1042 (2017) - 2015
- [c4]Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski:
Hybrid Hierarchical and Modular Tests for SoC Designs. NATW 2015: 11-16 - [c3]Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty:
ExTest scheduling for 2.5D system-on-chip integrated circuits. VTS 2015: 1-6 - 2013
- [c2]Guoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang:
Scan Test Data Volume Reduction for SoC Designs in EDT Environment. Asian Test Symposium 2013: 103-104 - 2012
- [c1]Guoliang Li, Jun Qian, Peter Li, Greg Zuo:
Multi-level EDT to Reduce Scan Channels in SoC Designs. Asian Test Symposium 2012: 77-82
Coauthor Index
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