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Pak K. Chan
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2000 – 2009
- 2003
- [c15]Pak K. Chan, Martine D. F. Schlag:
Parallel placement for field-programmable gate arrays. FPGA 2003: 43-50 - 2000
- [j11]Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 850-862 (2000) - [c14]Pak K. Chan, Martine D. F. Schlag:
New parallelization and convergence results for NC: a negotiation-based FPGA router. FPGA 2000: 165-174 - [c13]Pak K. Chan, Liter Siek, Hwee C. Tay, Jing H. Su:
A low-offset class-AB CMOS operational amplifier. ISCAS 2000: 455-458
1990 – 1999
- 1999
- [j10]Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan:
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1389-1399 (1999) - [c12]Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, Katsuharu Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu:
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM 1999: 308-309 - 1997
- [c11]Pak K. Chan, Martine D. F. Schlag:
Acceleration of an FPGA router. FCCM 1997: 175-181 - [c10]Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag:
Hybrid spectral/iterative partitioning. ICCAD 1997: 436-440 - 1996
- [j9]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral-based multiway FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 554-560 (1996) - [c9]Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan:
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. ICCAD 1996: 201-204 - 1995
- [c8]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral-Based Multi-Way FPGA Partitioning. FPGA 1995: 133-139 - [e1]Pak K. Chan, Jonathan Rose:
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995. ACM 1995, ISBN 0-89791-743-X [contents] - 1994
- [j8]Martine D. F. Schlag, Jackson Kong, Pak K. Chan:
Routability-driven technology mapping for lookup table-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 13-26 (1994) - [j7]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral K-way ratio-cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1088-1096 (1994) - 1993
- [j6]Martine D. F. Schlag, Pak K. Chan, Jackson Kong:
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 713-722 (1993) - [c7]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
On Routability Prediction for Field-Programmable Gate Arrays. DAC 1993: 326-330 - [c6]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral K-Way Ratio-Cut Partitioning and Clustering. DAC 1993: 749-754 - 1992
- [j5]Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija:
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41(8): 920-930 (1992) - [c5]Martine D. F. Schlag, Jackson Kong, Pak K. Chan:
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. ICCD 1992: 86-90 - 1991
- [j4]Pak K. Chan:
Comments on 'Asymptotic waveform evaluation for timing analysis'. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1078-1079 (1991) - [c4]Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija:
Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic 1991: 154-164 - 1990
- [j3]Pak K. Chan, Martine D. F. Schlag:
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. IEEE Trans. Computers 39(8): 983-992 (1990) - [j2]Pak K. Chan, Kevin Karplus:
Computing signal delay in general RC networks by tree/link partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 898-902 (1990) - [c3]Pak K. Chan:
Algorithms for Library-Specific Sizing of Combinational Logic. DAC 1990: 353-356
1980 – 1989
- 1989
- [j1]Pak K. Chan, Martine D. F. Schlag:
Bounds on signal delay in RC mesh networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6): 581-589 (1989) - [c2]Pak K. Chan, Martine D. F. Schlag:
Analysis and design of CMOS Manchester adders with variable carry-skip. IEEE Symposium on Computer Arithmetic 1989: 86-95 - [c1]Pak K. Chan, Kevin Karplus:
Computing Signal Delay in General RC Networks by Tree/Link Partitioning. DAC 1989: 485-490
Coauthor Index
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