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ORCIDMary L. Bailey
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- affiliation: University of Arizona, Tucson, USA
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1990 – 1999
- 1997
[j7]Prasenjit Sarkar, Mary L. Bailey:
Adapting the Network Interface for High-Performance Computing: The CNI Approach. J. Supercomput. 11(2): 181-200 (1997)- 1996
- [c12]Prasenjit Sarkar, Mary L. Bailey:
CNI: A High-Performance Network Interface for Workstation Clusters. HPDC 1996: 151-160 - [c11]Wilkey Richardson, Mary L. Bailey, William H. Sanders:
Using ZPL to Develop a Parallel Chaos Router Simulator. WSC 1996: 809-816 - 1994
- [j6]Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain:
Parallel Logic Simulation of VLSI Systems. ACM Comput. Surv. 26(3): 255-294 (1994) - [j5]Mary L. Bailey, Michael A. Pagels:
Empirical Measurements of Overheads in Conservative Asynchronous Simulations. ACM Trans. Model. Comput. Simul. 4(4): 350-367 (1994) - [c10]Mary L. Bailey, Burra Gopal, Michael A. Pagels, Larry L. Peterson, Prasenjit Sarkar:
PathFinder: A Pattern-Based Packet Classifier. OSDI 1994: 115-123 - [c9]Mary L. Bailey, Shane Walker:
Towards "on the fly" performance models for conservative asynchronous protocols. WSC 1994: 1431-1434 - 1993
- [j4]Mary L. Bailey:
A delay-based model for circuit parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1903-1912 (1993) - [c8]Mary L. Bailey, Michael A. Pagels, Kachung Kevin Wong:
How using busses in multicomputer programs affects conservative parallel simulation. PADS 1993: 93-100 - 1992
- [j3]Mary L. Bailey:
How circuit size affects parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 208-215 (1992) - [j2]Mary L. Bailey:
A time-based model for investigating parallel logic-level simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 816-824 (1992) - 1991
- [c7]Mary L. Bailey, Michael A. Pagels:
Measuring the overhead in conservative parallel simulations of multicomputer programs. WSC 1991: 627-636 - 1990
- [c6]Yi-Bing Lin, Edward D. Lazowska, Mary L. Bailey:
Comparing Synchronization Protocols for Parallel Logic-Level Simulation. ICPP (3) 1990: 223-227
1980 – 1989
- 1989
- [j1]Tony DeRose, Mary L. Bailey, Bill Barnard, Robert Cypher, David Dobrikin, Carl Ebeling, Smaragda Konstantinidou, Larry McMurchie, Haim Mizrahi, Bill Yost:
Apex: two architectures for generating parametric curves and surfaces. Vis. Comput. 5(5): 264-276 (1989) - [c5]Mary L. Bailey, Lawrence Snyder:
A model for comparing synchronization strategies for parallel logic-level simulation. ICCAD 1989: 502-505 - 1988
- [c4]Mary L. Bailey, Lawrence Snyder:
An Empirical Study of On-chip Parallelism. DAC 1988: 160-165 - [c3]Mary L. Bailey, David Socha, David Notkin:
Debugging Parallel Programs using Graphical Views. ICPP (2) 1988: 46-49 - [c2]David Socha, Mary L. Bailey, David Notkin:
Voyeur: Graphical Views of Parallel Programs. Workshop on Parallel and Distributed Debugging 1988: 206-216 - [c1]David Notkin, Lawrence Snyder, David Socha, Mary L. Bailey, Bruce Forstall, Kevin Gates, Raymond Greenlaw, William G. Griswold
, Thomas J. Holman, Richard Korry, Gemini Lasswell, Robert Mitchell, Philip A. Nelson:
Experiences with Poker. PPOPP/PPEALS 1988: 10-20
Coauthor Index
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