BibTeX records: Hung-Yu Li

• > Home > Persons > Hung-Yu Li

@inproceedings{DBLP:conf/iscas/YangLHLCCCHJLLLSWLH12,
  author       = {Hao{-}I Yang and
                  Yi{-}Wei Lin and
                  Mao{-}Chih Hsia and
                  Geng{-}Cing Lin and
                  Chi{-}Shin Chang and
                  Yin{-}Nien Chen and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Shyh{-}Jye Jou and
                  Nan{-}Chun Lien and
                  Hung{-}Yu Li and
                  Kuen{-}Di Lee and
                  Wei{-}Chiang Shih and
                  Ya{-}Ping Wu and
                  Wen{-}Ta Lee and
                  Chih{-}Chiang Hsu},
  title        = {High-performance 0.6V {VMIN} 55nm 1.0Mb 6T {SRAM} with adaptive {BL}
                  bleeder},
  booktitle    = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  2012, Seoul, Korea (South), May 20-23, 2012},
  pages        = {1831--1834},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISCAS.2012.6271624},
  doi          = {10.1109/ISCAS.2012.6271624},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/YangLHLCCCHJLLLSWLH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/YangYHLLCCLCCHJLLLSWLH11,
  author       = {Hao{-}I Yang and
                  Shih{-}Chi Yang and
                  Mao{-}Chih Hsia and
                  Yung{-}Wei Lin and
                  Yi{-}Wei Lin and
                  Chien{-}Hen Chen and
                  Chi{-}Shin Chang and
                  Geng{-}Cing Lin and
                  Yin{-}Nien Chen and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Shyh{-}Jye Jou and
                  Nan{-}Chun Lien and
                  Hung{-}Yu Li and
                  Kuen{-}Di Lee and
                  Wei{-}Chiang Shih and
                  Ya{-}Ping Wu and
                  Wen{-}Ta Lee and
                  Chih{-}Chiang Hsu},
  title        = {A high-performance low {VMIN} 55nm 512Kb disturb-free 8T {SRAM} with
                  adaptive {VVSS} control},
  booktitle    = {{IEEE} 24th International SoC Conference, {SOCC} 2011, Taipei, Taiwan,
                  September 26-28, 2011},
  pages        = {197--200},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/SOCC.2011.6085080},
  doi          = {10.1109/SOCC.2011.6085080},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/YangYHLLCCLCCHJLLLSWLH11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LiCWY06,
  author       = {Hung{-}Yu Li and
                  Chia{-}Cheng Chen and
                  Jinn{-}Shyan Wang and
                  Chingwei Yeh},
  title        = {An AND-type match-line scheme for high-performance energy-efficient
                  content addressable memories},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {41},
  number       = {5},
  pages        = {1108--1119},
  year         = {2006},
  url          = {https://doi.org/10.1109/JSSC.2006.872719},
  doi          = {10.1109/JSSC.2006.872719},
  timestamp    = {Fri, 15 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LiCWY06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/WangLYC05,
  author       = {Jinn{-}Shyan Wang and
                  Hung{-}Yu Li and
                  Chingwei Yeh and
                  Tien{-}Fu Chen},
  title        = {Design techniques for single-low-V\({}_{\mbox{DD}}\) {CMOS} systems},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {40},
  number       = {5},
  pages        = {1157--1165},
  year         = {2005},
  url          = {https://doi.org/10.1109/JSSC.2005.845979},
  doi          = {10.1109/JSSC.2005.845979},
  timestamp    = {Mon, 14 Mar 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/WangLYC05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jise/WuCLW03,
  author       = {Hung{-}Cheng Wu and
                  Tien{-}Fu Chen and
                  Hung{-}Yu Li and
                  Jinn{-}Shyan Wang},
  title        = {Energy Efficient Caching-on-Cache Architectures for Embedded Systems},
  journal      = {J. Inf. Sci. Eng.},
  volume       = {19},
  number       = {5},
  pages        = {809--825},
  year         = {2003},
  url          = {http://www.iis.sinica.edu.tw/page/jise/2003/200309\_05.html},
  timestamp    = {Fri, 16 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jise/WuCLW03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/WangTL00,
  author       = {Jinn{-}Shyan Wang and
                  Wayne Tseng and
                  Hung{-}Yu Li},
  title        = {Low-power embedded {SRAM} with the current-mode write technique},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {35},
  number       = {1},
  pages        = {119--124},
  year         = {2000},
  url          = {https://doi.org/10.1109/4.818929},
  doi          = {10.1109/4.818929},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WangTL00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}