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ORCIDIntegration, Volume 54
Volume 54, June 2016
- Muhammad E. S. Elrabaa, Amran Al-Aghbari
, Mohammed Alasli, Aiman El-Maleh, Abdelhafid Bouhraoua, Mohammad R. Alshayeb:
A low-cost platform for the prototyping and characterization of digital circuit IPs. 1-9 - Gian Domenico Licciardo, Thomas Boesch, Danilo Pau, Luigi Di Benedetto:
Frame buffer-less stream processor for accurate real-time interest point detection. 10-23 - Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. 24-36 - Basant Kumar Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, M. N. S. Swamy:
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. 37-46 - Marzieh Ranjbar Pirbasti, Mahdi Fazeli, Ahmad Patooghy:
Phase Change Memory lifetime enhancement via online data swapping. 47-55 - Yansong Gao, Omid Kavehei, Said F. Al-Sarawi, Damith Chinthana Ranasinghe, Derek Abbott:
Read operation performance of large selectorless cross-point array with self-rectifying memristive device. 56-64 - Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin, Nor Hisham Hamid:
Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services. 65-96 - Geunho Cho, Fabrizio Lombardi:
Design and process variation analysis of CNTFET-based ternary memory cells. 97-108 - Pinaki Mazumder, D. Hu, Idongesit E. Ebong, Xu Zhang, Z. Xu, Silvia Ferrari:
Digital implementation of a virtual insect trained by spike-timing dependent plasticity. 109-117
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