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ORCID28th VDAT 2024: Vellore, India
- 28th International Symposium on VLSI Design and Test, VDAT 2024, Vellore, India, September 1-3, 2024. IEEE 2024, ISBN 979-8-3503-8010-1
- Manjith Baby Sarojam Chellam, Ramasubramanian Natarajan, Nagi Naganathan:
Secure key exchange protocol and storage of logic locking key. 1-6 - Sridhar P
, Harish Mallikarjun Kittur, Arghya Korantak, Akshat Kumar:
An Adaptive Multi-Objective Optimization on CMOS Two Stage Op-Amp Circuit Synthesis. 1-8 - Ashish Verma, Preeti Verma, Vaithiyanathan Dhandapani:
Comparative Study Of GAA-JL Transistor With And Without FE Material For Hydrogen Gas Sensing. 1-6 - Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine:
Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing. 1-6 - Aryan Kannaujiya, Vipul Sahu, Ambika Prasad Shah:
High-Performance Stacked Dynamic Comparator for Analog to Digital Converters. 1-6 - Gummuluri Pavan Kumar, Manas Ranjan Tripathy, Jogendra Singh Rana, Harshit Srivastava, BSS Tejesh, Satyabrata Jit:
A Deep Insight into Frequency and Voltage Variation Impact on Memristor Performance and Applications of Memristor-NMOS Hybrid Structure in the Digital Domain. 1-6 - Sudhakar Reddy Dantla, Prudhvi Tummala, Hemanth Danaboina, Jaswanth Kumar Ghantasala, Sarada Musala, Pitchaiah Telagathoti:
FPGA Implementation of Energy Efficient Approximate Hybrid Parallel Prefix Adders for Image Processing Applications. 1-6 - Md. Sifatul Muktadir, Bhubon Chandra Mech, Rajesh Kumar Singh:
Analytical investigation of the Drain Current and Surface Potential in NC- FETs considering the doping concentration and Interface Trap Charge Effect. 1-4 - Lokenath Kundu, Subhanil Maity, Sourav Nath, Gaurav Singh Baghel, Krishna Lal Baishnab:
A Design Approach for ZigBee Compatible CML-based 2/3 Dual Modulus Frequency Divider. 1-6 - Munindra, Banoth Krishna, Dava Nand:
Capacitive Nonlinearity of GFET Compact Model in Quasi-Ballistic Regime for High-Frequency Applications. 1-5 - Lourdu Jennifer J. R, Joy Vasantha Rani S. P:
Enhanced Edge Detection for Image Segmentation and its Real-Time Implementation. 1-6 - Md. Kashif Khan, Nidhee Bhuwal, Sagar Sagar, Deepika Gupta:
Meminductor Emulator via Flux Approach for Wide Frequency Range Applications. 1-6 - Moitreya Chaudhury, Binit Kumar Pandit, Ayan Banerjee:
A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans. 1-6 - Ritaja Das, Priyank Kalla:
Selecting Rectification Targets for Patching Buggy Circuits. 1-6 - M. Mohamed Asan Basiri:
Low Latency VLSI Architecture of Histogram Equalization of Images. 1-6 - Balkrishna Choubey, Kankat Ghosh:
Impact of SRH Lifetime on the Performance of Aluminium Gallium Nitride Based Ultraviolet -C Light Emitting Diodes. 1-4 - Soumita Chatterjee, Soumya Pandit, Arpita Das:
Design of FPGA based Custom IP Core to Detect the Edges of Brain Tumors. 1-6 - Aprajita Bera, Sudhakar Mande:
Machine Learning Based Computationally Efficient Approach for Accurate Prediction of Power Integrity Performance of Power Distribution Networks. 1-5 - Muhammed Raees P. C, Akshayraj M. R, Varun P. Gopi, G. Lakshminarayanan, G. R. Gangadharan, Jayaraj U. Kidav:
Dynamic Precision Scaling in MAC Units for Energy-Efficient Computations in Deep Neural Network Accelerators. 1-7 - Priyanka P, Ashwin Kumar Narasimhan, Hema Brindha M, Angeline Kirubha S. P:
Pioneering accessibility: Development of a cost-efficient optical imaging system. 1-7 - Patel Rutvikkumar Popatbhai, Ruchi Gajjar:
Runtime Prediction for VLSI Physical Design Processes using Machine Learning. 1-6 - Ganpat Anant Parulekar, Shalabh Gupta:
A PAM-4 Based Full Duplex IO with In-built Feed-Forward Equalizer and Performance Enhanced Receiver. 1-5 - Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine:
A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications. 1-6 - Vishal Gupta, Sribhuvaneshwari H, Tanmaya Kumar Das, Saurabh Khandelwal, Shyam Akashe:
Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design. 1-5 - Munazir Reza, Naushad Alam, Syed Javed Gaggatur:
A 0-24mA, 1.2V/1.8V Dual Mode Low Dropout Regulator Design for Efficient Power Management in Battery-Powered Systems. 1-6 - Jasleen Kaur Ahuja, Archita, Hari Priya Raveendran:
Simulation based methodology for fault analysis of PCB designs. 1-6 - Deepika Kumaradasan, Sougata Kumar Kar, Santanu Sarkar:
A Low-Power 10-bit SAR ADC with an Integrated CDAC and C-MOSCAP DAC for Implantable Pacemakers. 1-6 - Arun Kumar Sinha, Sri Lakshmi Sangam:
A TCAD Performance Analysis of an Inverter with 80% Non-Alignment in Gate in sub-45 nm Technology. 1-6 - P. Saravanan, Harreni V, Krishnaveni V:
Three Stage Operational Amplifier with Split Length Differential Input Pair for IoT Applications. 1-6 - Sri Sakthi Santhanam, Ankita Dhole, Sudheer Anumala:
Generic methodolgy and solution for Additive Jitter correction in Mesh based clock architectures. 1-6 - Purvi Patel, Biswajit Mishra:
Energy Harvester Powered On-chip Reconfigurable Switched Capacitor Converter in 0.18 μm CMOS. 1-6 - Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Vadthya Bheemudu, Shubham Tayal, Vadthiya Narendar:
Study of HeavyIon Irradiation Effects in FinFETs at Sub-5 nm Technology Node: Reliability Perspective. 1-5 - Navneet Gandhi, Rajeewa Kumar Jaisawal, P. N. Kondekar, Ankit Dixit, Naveen Kumar, Vihar P. Georgiev, Navjeet Bagga:
Demonstration of a Vertically Stacked Junctionless Forksheet as Dielectric Modulated Biosensor. 1-4 - Omkar Kokane, Prabhat Sati, Mukul Lokhande, Santosh Kumar Vishvakarma:
HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine. 1-6 - Gulafsha Bhatti, Yash Agrawal, Vinay S. Palaparthy:
Signal Integrity Assessment of Stretchable Interconnects for Flexible Electronics System. 1-6 - R. Sai Meghana, Meghana Kulkarni:
Smart System with Descriptive Video Service and Spoken Dialogue System for Visually Impaired Individuals. 1-6 - S. Deepanjali, Noor Mahammad Sk, Raghavendra Kumar Sakali:
Fault Resilient Micro-Coded Control Unit for Space-Based Digital Systems. 1-6 - Farook Basha Shaik, Manish Kashyap:
Classification Algorithm for VLSI Test Cost Reduction. 1-5 - B. Naresh Kumar Reddy, Srinivasulu Jogi, Sarangam K:
Design and Implementation of an FPGA-based Emulator Circuit for MLP using Memristors. 1-6 - Dinesh Sai Ganapathi Mavuri, Roshni Oommen, Aswathi R. Nair:
Influence of Synaptic Device Properties on the Performance of Artificial Neural Networks. 1-5 - Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Sri Parameswaran, Soumya J.:
Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA. 1-6 - Sarath Kumar K, Akash Iyer, Swastik Raj Behera, K. Sivasankaran:
Surface Drift Debris Segmentation and Visualization through YCbCr Colour Space Thresholding using Low Power FPGA. 1-5 - George Joseph, E. P. Jayakumar:
Quantized Neural Network Architecture for Hardware Efficient Real-Time 4K Image Super-Resolution. 1-5 - Hirak Jyoti Chakraborty, Deep Ketankumar Acharya:
A Shift-left Approach in Qualification of Digital IPs for SoCs by Applying Advanced Automation and Data Analytics. 1-5 - Koraboyina Anusha, R. NandaKumar:
Design, Validation and Characterization of Number Theoretic Transform IP Core. 1-6 - Prabhat Kumar Barik, Barathram Ramkumar:
Low-offset Voltage Error and Low Noise Based CMOS Push-pull Operational Amplifier for Biomedical Applications in 180-nm CMOS Technology. 1-5 - Venkata Appa Rao Yempada, Srivatsava Jandhyala, Janamani Chandram Ayyangalam:
>Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs. 1-5 - Raju Vemuri, Saurabh Nagar:
Impact of Compliance Current on the Switching Behavior in SiOx based Resistive Switching Devices. 1-4 - Sandra Sugathan, Adersh V. R:
Optimized Test Pattern Generation for Digital Circuits using SAT-Based ATPG and Scan Insertion Method. 1-6 - Maitri Iyer, Rishav Bhowmick, Harsh Singh, Jai Gopal Pandey:
Security Assessment of Rotation Countermeasure for Protection Against Fault Attacks. 1-6 - Neha Agrawal, Amit Kumar, Hitesh Marwah:
Optimizing Concurrent Co-Designing of ICs and Package using Multi Technology and RF Solution. 1-4 - Ashish Maurya, Shailendra Yadav, Sagar, Kaushal Kishor, Gyanendra Kumar Verma:
2D-Transitional Metal Dichalcogenide Materials for Bio-sensors Application: A DFT-based approach. 1-5 - Puja Kumari, Rahul Bhattacharya:
MATLAB-Simulink based Framework for Combinational ATPG Applied to Testing of Digital Blocks in Analog and Mixed-Signal Circuits. 1-6 - Sourav Nath, Lokenath Kundu, Koushik Guha, Krishna Lal Baishnab:
Design and Analysis of Cross-Coupled Source Degenerated Balanced OTA for Biomedical Application. 1-6 - Tanay Das, Madhav Pathak, Sandip Lashkare:
Dynamic Resistance Reduction Methods for Voltage Clamp Lowering to Enhance GGNMOS ESD Protection. 1-5 - A. V. Arun, Sreelekshmi P. S, Jobymol Jacob:
Implementation of an Efficient Charge Pump using Gate All Around Nanowire TFET for Energy Harvesting Applications. 1-6 - Bana Shanmuga Sai Badrinatha Reddy, Priya K, Binsu J. Kailath:
SNN with Gradient-based Backpropagation algorithm for ECG arrhythmia classification with LIF neuron and AdEx neuron. 1-6 - Shraman Biswas, Soumya Pandit, Arpita Das:
Design of A Custom IP Core for Concatenated SVM Model to Classify Multi-class Handwritten Numerical Characters. 1-6 - Naveen R, Sudhish N. George:
Power Efficient ASIC Design for Vision Transformer using Systolic Array Matrix Multiplier. 1-6 - N. R. Sivaraaj, K. K. Abdul Majeed:
Design and Implementation of High Performance CMOS Cross-Coupled LCVCO for Low Phase Noise. 1-6 - Chintan M. K, Rashmi Seethur:
A 10-bit 0.9-GS/s Segmented Flash ADC. 1-6 - Sourodeep Kundu, Subham Kumar, Laxmidhar Biswal, Chandan Bandyopadhyay, Anirban Bhattacharjee, Hafizur Rahaman:
An Improved Circuit Transformation Technique for Nearest Neighbor Implementation of Quantum Circuits. 1-6 - Indranil Maity, Soubarno Chatterjee, Souvik Bhanja:
Acetone Sensing Performance of Pristine and Gold Doped Graphene Sheet: A Comparative Analysis. 1-6 - Akshayraj M. R, Muhammed Raees P. C, Varun P. Gopi, G. Lakshminarayanan, G. R. Gangadharan, Jayaraj U. Kidav:
Energy-Efficient Hardware Design for CNN-Based ECG Signal Classification in Wearable Bio-Medical Devices. 1-7 - Pragnya Dhal, Arighna Deb, Subrata Das, Debesh Kumar Das:
Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars. 1-7 - Snehalatha Lalithamma, Saravana Manivannan, Uddipan Agasti:
Analysis of Device Noise in Bandgap Reference Voltage Generators. 1-7 - Pankaj Nair V. M, Lalu V:
Design and Implementation of 5-Stage Pipelined RISC-V Processor on FPGA. 1-6 - Hari Shanker Gupta, Singh Shruti Satyendra, Bhumika Deo, Rane Prathamesh Santosh, Ritesh Khole, Varun Dev Singh, Nishant Kumar, Krish Prakash:
Design and Analysis of 8T Radiation Hardened SRAM using 65nm Process. 1-4 - Jatin Chakravarti, Chintan Panchal:
Test Time Reduction with Data Throttling Techniques in a Multi Core SoC Design. 1-4 - Suraj Paul:
An Adaptive Strategy for Dynamic Resource Allocation and Scheduling for Multitasking NoC based Multicore Systems. 1-6 - Arjun J. M, Titto Anujan:
Design and ASIC Implementation of Area Efficient UART Core in SCL 180nm Technology. 1-5 - Dhruva S. Hegde, Mandar Datar, Manish Prajapati, Sachin B. Patkar, Gaurav Trivedi:
Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow. 1-6
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