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ORCIDSantanu Sarkar 0002
Person information
- affiliation: Indian Institute of Technology, Kharagpur, India
Other persons with the same name
- Santanu Sarkar — disambiguation page
- Santanu Sarkar 0001
![[0000-0001-6821-920X]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-6821-920X")
— Indian Institute of Technology Madras, Chennai, India (and 1 more)
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2020 – today
- 2022
[j2]Smrutilekha Samanta, Santanu Sarkar:
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1332-1340 (2022)
2010 – 2019
- 2015
- [c4]Santanu Sarkar, Swapna Banerjee:
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. ISVLSI 2015: 172-177 - 2014
- [j1]Santanu Sarkar, Swapna Banerjee:
An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters. Microelectron. J. 45(6): 666-677 (2014)
2000 – 2009
- 2009
- [c3]Santanu Sarkar, Swapna Banerjee:
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. ISVLSI 2009: 268-273 - 2008
- [c2]Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee:
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. ISCAS 2008: 149-152 - 2006
- [c1]Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee:
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. APCCAS 2006: 1-4
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