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ORCID38th SBCCI 2025: Manaus, Brazil
- 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, SBCCI 2025, Manaus, Brazil, August 25 - Sept. 1, 2025. IEEE 2025, ISBN 979-8-3315-5555-9
- Byron Tarabata, Eduardo Holguín, Martín Gavilánez, Esteban Astudillo, Ana Salcedo, Luis Miguel Prócel:
Silicon-Proven Synchronous and Asynchronous Frequency-to-Digital Converters Using Open-Source EDA Tools. 1-6 - Morgana M. A. da Rosa, Rodrigo Lopes, Eduardo A. C. da Costa, Rafael Soares:
A Cross-Layer Approximate Kernel for Gaussian Filtering. 1-5 - Lucas Daudt Franck, Hamilton Duarte Klimach, Sandro Binsfeld Ferreira:
An 8-bit Digitally-Controlled Ring Oscillator with Feedback-Enhanced Current Regulation. 1-5 - Thiago C. A. Paschoalin, Ualison R. F. Dias, Melissa S. Aguiar, Dabson F. Dos Santos, Tiago M. Quirino, Luciano M. De Andrade Filho:
Uncorrelated Pseudo-Random Generator for FPGA. 1-5 - Vanessa M. Da F. Botinelly, Filipe F. Caetano, Osamu Saotome, Lucas Compassi Severo:
A 5.8-GHz ULV Active-Biased LNTA Designed using Tradeoff-Based Biasing Metric. 1-5 - Leonardo D. Sanabria, Fernanda D. V. R. Oliveira, Fernando A. P. Barúqui, Fabian Olivera, Nelson Maculan:
Violation Constraint-Handling Genetic Algorithm for Fully-Differential OTA Design Optimization. 1-5 - Leonardo Müller, Daiane Freitas, Patrick Rosa, Cláudio Machado Diniz, Mateus Grellert, Guilherme Corrêa:
Learning-Based Operand Isolation for Power-Aware Hardware Design of AV1 FME/MC Interpolation. 1-5 - Vítor Costa, Murilo R. Perleberg, Luciano Agostini, Marcelo Schiavon Porto:
Efficient Hardware Design for Compressed Blocks SAD Calculation in VVC Motion Estimation. 1-5 - Rodrigo Lopes, Victor Santos, Leonardo Antonietti, Morgana da Rosa, Eduardo A. C. da Costa, Rafael Soares:
ARL-4AC: Approximate Recombination Line in Approximate 4-2 Adder Compressor. 1-5 - Arthur F. Ely, Ian Kersz, Michael G. Jordan, José Rodrigo Azambuja, Antonio Carlos S. Beck, Fernanda Lima Kastensmidt:
HARA: Hardware-Aware Resource Allocation for FPGA-Based Neural Network Acceleration. 1-5 - Raphael Cardoso, Fábio Rabuske, Tiago R. Balen, Hamilton Klimach, Sergio Bampi:
A Resistorless Low-Power Differentiator for MPPT Adjustment of Energy Harvesting Systems. 1-5 - Morgana M. A. da Rosa, Eduardo A. C. da Costa, Rafael Soares:
Approximate Radix-2m Bit-Leading-Based Adder. 1-5 - Pedro Aquino Silva, Pedro Paiva, Melissa Vetromille, Mateus Grellert:
Open-Source Verification IP for AXI-Stream. 1-5 - Hércules Leonel, Willian Analdo Nunes, Fernando Gehm Moraes:
PPA Evaluation of Hardware Accelerated AES Algorithm Using RISC-V ISE. 1-5 - Jorge Marin, Krzysztof Herman, Daniel Arévalos, Martin Andraud, Christian A. Rojas:
Tapeout-Oriented Strategies for Teaching Analog/Mixed-Signal IC Design and Implementation in Electrical Engineering Education. 1-5 - Lucas Conde, Marenice Carvalho, José Andrade, Fernando Chavez:
A Modular Power Switches Layout Strategy to a SiC Gate Driver Development. 1-5 - Rodrigo Feldens, Sergio Bampi, Felipe Sampaio:
Complexity Optimization Based on Decision Trees of Inter-Frame Prediction in VVC Encoders. 1-5 - Matheus B. S. Carvalho, Crístian Müller, Alessandro Gonçalves Girardi, Paulo César Comassetto de Aguirre:
Digital Correction of Residue Amplifier Gain Error in a Two-Stage Pipeline-SAR ADC. 1-5 - Marina Longo Dias, Paulo F. Butzen, Ricardo Reis, Cristina Meinhardt:
Impact of Circuit-Level Radiation-Hardening Techniques in Adders on a RISC-V Design. 1-5 - Nicolas De Carvalho, Lucas Nogueira, Marcus Anderson, David C. C. Freitas, Jarbas Aryel Nunes da Silveira, César A. M. Marcon:
Improving Error Correction Efficacy by Applying Nesting Encoding Approach. 1-5 - Emanuel V. C. Ruella, João Gabriel O. Bicalho, Ricardo S. Ferreira, Omar P. Vilela Neto, José Augusto Miranda Nacif:
A Comprehensive Analysis of Wire Performance in Silicon Dangling Bonds. 1-5 - Matheus Carvalho, Renan Neves Da Silva, Samuel Souza Da Silva, Janier Arias-Garcia, Lucas Giovani Nardo:
Image Steganography Based on Chaotic Systems and Finite-Precision Error. 1-5 - Lucas Nogueira, F. Mirailton, Danilo Alencar, J. Alisson, Jardel Silveira, Jarbas Silveira, Fabian Vargas:
Auto-Tuning Aging Sensor Validated Under Burn-In, Temperature, and Voltage Variations. 1-5 - Társio Onofrio Da Silva, Fernando Gehm Moraes:
Fast and Energy-Efficient 2D Convolution: Inspection-Based Methods for Hardware Acceleration. 1-5 - Régis Leveugle, Ahmed Al Kaf, Mounir Benabdenbi:
Edge AI Dependability: Is Bit-flip Direction the Right Concern in Trustworthiness Reinforcement? 1-5 - Luís Fernando L. França, Fabio Benevenuti, Leonardo R. Gobatto, Antonio Carlos S. Beck, José Rodrigo Furlanetto Azambuja, Fernanda Lima Kastensmidt:
Failure Assessment of NASA cFS Case-Study Flight Software on RISC-V via Fault Injection. 1-5 - Eric Friedrich, André Regis, Pedro Paiva, Mateus Grellert:
VLSI Design of a Fast and Reprogrammable Decision Tree Inference Accelerator. 1-5 - Eloisa Barros, Rodrigo Lopes, Morgana da Rosa, Eduardo Da Costa, Rafael Soares:
A Low-Power and Area-Efficient Architecture for Hyperbolic CORDIC with Enhanced Accuracy. 1-5 - Leonardo Gobatto, Fabio Benevenuti, Luiz Henrique Laurini, Benjamin Cheymol, Rodrigo Possamai Bastos, Fernanda L. Kastensmidt, José Rodrigo Azambuja:
Impact of Register Reservation on the Reliability of Arm Cortex-M Processors under Neutrons. 1-5 - Kauana Quintana Fort, Maurício Banaszeski Da Silva, Kliver Barboza Alves, João Baptista Dos Santos Martins:
Low-Power Synthesis of a Digital Frequency-Locked Loop. 1-5 - Vitor H. Fuerstenau, Felipe T. Bortolon, Marcos Backes, Eduardo Barbian, Ricardo Reis:
Transistor Placement Routability Prediction for Standard Cell Design. 1-5 - Gabriel Bitencourt Cardoso, Jiovana Sousa Gomes, Ricardo Peixoto Robaina, Sergio Bampi, Fábio Luís Livi Ramos:
NNCodec Neural Network Compression Assessment and Binarization Step Hardware Design. 1-5 - Alexandre Zem De Morais, André Augusto Mariano, Bernardo Leite:
CMOS Power Amplifiers for X-Band: A Survey. 1-5 - Gabriel Rosa Dias, Jiovana Sousa Gomes, Sergio Bampi, Fábio Luís Livi Ramos:
Design Landscape of VVC Binary Arithmetic Decoder using Multiple Bypass Bins Processing. 1-5 - Marc Neu, Isabel Haide, Timo Justinger, Till Rädler, Valdrin Dajaku, Torben Ferber, Jürgen Becker:
Real-Time Graph-based Point Cloud Networks on FPGAs via Stall-Free Deep Pipelining. 1-5 - Yasmin Camargo, Matheus Isquierdo, Daniel Palomino, Bruno Zatt, Felipe Sampaio:
Dynamic Approximate Storage Scheme for VVC Intra-Frame Prediction. 1-5 - Leonardo Silveira, Samuel Wachholz, Leonardo Antonietti, Morgana da Rosa, Eduardo Da Costa, Sérgio Almeida, Rafael Soares:
RASC: A Low-Power Reconfigurable 4-2 Adder-Subtractor-Compressor. 1-5 - Matheus Isquierdo, Felipe Sampaio, Bruno Zatt, Nikil D. Dutt, Daniel Palomino:
Employing Approximate Storage for Rate-Distortion Optimization in VVC Encoders. 1-5 - Emilia Casares López, José Montahuano, Esteban Astudillo, Eduardo Holguín:
Process Variation Sensing and Compensation Employing a Ring Oscillator-Based Architecture in SkyWater 130nm Technology. 1-5 - Patrick Rosa, Daiane Freitas, Leonardo Müller, Guilherme Corrêa, Daniel Palomino:
Fast Interpolation Filter Decision using Machine Learning for the Fractional Inter-Prediction of AV1. 1-5 - Ana Paula Salcedo, Eduardo Holguín, Luis-Miguel Procel:
Segmented Precharge Free Content Addressable Memory for Energy Efficiency. 1-5 - Ramiro Viana, Marta Loose, Marcelo Schiavon Porto, Guilherme Corrêa, Luciano Agostini:
Fast VVC Affine Motion Estimation Using a Hardware-Friendly Machine Learning Method. 1-5 - Fabricio Lorenzon, Lorenzo Nemitz, Mateus Grellert:
Design and Synthesis of Row-Stationary Hardware Accelerators for 2D Convolution. 1-5 - Ruhan A. Conceição, Denis Maass, Vanessa Aldrighi, Wen-Hsiao Peng, Marcelo Schiavon Porto, Luciano Agostini:
Platform-Independent Hardware Design for Low-Power Neural Video Hyperprior Decoding. 1-5 - Rafael O. Nunes, Antonio C. C. Telles, M. C. Carlos, W. R. Melo, Saulo Finco, Luis Eduardo Seixas Jr.:
AI-Driven Optimization of Sigma-Delta ADCs for Space Applications. 1-5 - Lucas M. Leipnitz de Fraga, Cláudio Machado Diniz:
Design and Analysis of Approximate Hardware Accelerators for VVC Intra Angular Prediction. 1-5 - Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, Vaisakh Naduvodi Viswambharan, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon:
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification. 1-5 - Ian Kersz, Pedro Alles, Ian R. Nodari, Arthur F. Ely, Michael G. Jordan, José Rodrigo Azambuja, Fernanda Lima Kastensmidt, Antonio Carlos S. Beck:
Exploring Adaptive Design Mapping and Device Activation in Multi-FPGA Edge Environments. 1-5 - Augusto Kessler Pires, Nathan Guimarães, Fernanda Kastensmitd, Antonio Carlos S. Beck, Mateus Grellert, José Rodrigo Azambuja:
Physical Implementation of the NoX RISC-V Core Using an Open PDK. 1-5 - Yingchun Lu, Hongliang Lu, Yujie Liu, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Xiumin Xu, Liang Yao:
Design of a Dynamic Obfuscation-Based Strong PUF Resistant to Modeling Attacks. 1-5 - Marcelo K. Moori, Hiago Mayk G. de A. Rocha, Antonio Carlos S. Beck:
Energy-Efficient Execution of Parallel Regions on Heterogeneous Multi-Cores. 1-5 - Vítor De M. Mandowski, Pedro T. L. Pereira, Paulo F. Butzen, Sergio Bampi, Leomar Soares da Rosa Júnior:
Approximate Adders for Efficient Circuits: Advantages and Limitations Compared to RCA. 1-5 - César Augusto Marcelo Albuquerque, Gabriel Maranhão, Deni Germano Alves Neto, Augusto Paulo Franco, Márcio Cherem Schneider:
A 1-MHz, 24-ppm/°C fully-integrated RC relaxation clock reference using 180 nm open-source PDK. 1-4 - Marcello M. Muñoz, Denis Maass, Murilo R. Perleberg, Luciano Agostini, Guilherme Corrêa, Marcelo Schiavon Porto:
Real-Time UHD 4K Hardware Design for the Gradient-Based Search of the VVC Affine ME. 1-5 - Tiago Oliveira Weber, Fabián Leonardo Cabrera:
Novel Simplified Analog Neuron in CMOS Technology with Digital Weights. 1-5 - Renan D. P. de Oliveira, Lucas Compassi Severo, Alessandro Girardi, Paulo César Comassetto de Aguirre:
A 125-kHz 4th-order Continuous-Time Sigma-Delta Modulator with Single Amplifier Resonator. 1-5 - Rafael Follmann Faccenda, Willian Analdo Nunes, Angelo Dal Zotto, Carlos Gabriel de Araujo Gewehr, Lucas Luza, Lucas Damo, Vitor Balbinot Zanini, Eduardo Bernardon, Vinícius Mibielli, Nathan Cidal, Fernando Gehm Moraes:
RS5-SoC: A Flexible Open-Source RISC-V Platform for Embedded Systems. 1-5 - Jéssica Gonsalves Santos, Ismael de Almeida Junior, Sylvain Engels, Robin Wilson, Laurent Fesquet:
Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits. 1-5 - Angelo Elias Dalzotto, Fernando Gehm Moraes:
Lightweight Machine-Learning-driven Security Threat Detection in NoC-based Manycores. 1-5
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last updated on 2025-11-18 22:36 CET by the dblp team
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