default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID12th NOCS 2018: Torino, Italy
- Zhonghai Lu, Sriram R. Vangal, Jiang Xu, Paul Bogdan:
Twelfth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Torino, Italy, October 4-5, 2018. IEEE 2018, ISBN 978-1-5386-4893-3
Keynotes
- Vivek De:
Keynote Talk: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities. 1 - Giovanni De Micheli:
Keynote Talk: NoCs: A Short History of Success and a Long Future. 1-2
Regular Papers
- Davide Giri, Paolo Mantovani, Luca P. Carloni:
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators. 1:1-1:8 - Subodha Charles, Chetan Arvind Patil
, Ümit Y. Ogras, Prabhat Mishra:
Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs. 2:1-2:8 - Dimitris Giannopoulos, Nikos Chrysos, Evangelos Mageiropoulos, Giannis Vardas, Leandros Tzanakis, Manolis Katevenis:
Accurate Congestion Control for RDMA Transfers. 3:1-3:8 - Abhishek Vashist, Amlan Ganguly, Mark A. Indovina:
Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects. 4:1-4:8 - Sebastian Werner, Pouya Fotouhi, Roberto Proietti, Xian Xiao, S. J. Ben Yoo:
Towards Energy-Efficient High-Throughput Photonic NoCs for 2.5D Integrated Systems: A Case for AWGRs. 5:1-5:8 - Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. 6:1-6:8 - Venkata Yaswanth Raparti, Sudeep Pasricha:
DAPPER: Data Aware Approximate NoC for GPGPU Architectures. 7:1-7:8 - Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis:
FreewayNoC: A DDR NoC with Pipeline Bypassing. 8:1-8:8 - Mayank Parasar, Ankit Sinha, Tushar Krishna:
Brownian Bubble Router: Enabling Deadlock Freedom via Guaranteed Forward Progress. 9:1-9:8 - Sourav Das, Kanad Basu, Janardhan Rao Doppa, Partha Pratim Pande, Ramesh Karri, Krishnendu Chakrabarty:
Abetting Planned Obsolescence by Aging 3D Networks-on-Chip. 10:1-10:8 - Chaochao Feng, Zhenyu Zhao, Zhuofan Liao, Xiaowei He:
A Low-Overhead Multicast Bufferless Router with Reconfigurable Banyan Network. 11:1-11:8 - Abhijit Das, Sarath Babu, John Jose, Sangeetha Jose, Maurizio Palesi:
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. 12:1-12:8 - Joel Ortiz Sosa, Olivier Sentieys, Christian Roland:
A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment. 13:1-13:8
Special Session Papers
- Travis H. Boraten, Avinash Karanth Kodi:
Securing NoCs Against Timing Attacks with Non-Interference Based Adaptive Routing. 14:1-14:8 - Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat:
Securing Photonic NoC Architectures from Hardware Trojans. 15:1-15:8 - Brian Lebiednik, Sergi Abadal, Hyoukjun Kwon, Tushar Krishna:
Architecting a Secure Wireless Network-on-Chip. 16:1-16:8 - Xiaohang Wang, Amit Kumar Singh, Shengyan Wen:
Exploiting Dark Cores for Performance Optimization via Patterning for Many-core Chips in the Dark Silicon Era. 17:1-17:8 - Arash Firuzan, Mehdi Modarressi, Masoud Daneshtalab, Midia Reshadi:
Reconfigurable Network-on-Chip for 3D Neural Network Accelerators. 18:1-18:8 - Ihsan El Masri, Pierre-Marie Martin, Hemanta Kumar Mondal, Rozenn Allanic, Thierry Le Gouguec, Cédric Quendo, Christian Roland, Jean-Philippe Diguet:
Accurate Channel Models for Realistic Design Space Exploration of Future Wireless NoCs. 19:1-19:8 - Xavier Timoneda, Albert Cabellos-Aparicio, Dionysios Manessis, Eduard Alarcón, Sergi Abadal:
Channel Characterization for Chip-scale Wireless Communications within Computing Packages. 20:1-20:8 - Sri Harsha Gade, Sidhartha Sankar Rout, Sujay Deb:
On-Chip Wireless Channel Propagation: Impact of Antenna Directionality and Placement on Channel Performance. 21:1-21:8
Tutorial Abstracts
- Jie Han:
Approximate Arithmetic Circuits and Their Applications. 22:1 - Eun Jung Kim:
Approximate Networks on Chip. 23:1
Industrial Session Abstracts
- Francesc Guim:
Challenges and Opportunities for Edge Cloud Architectures. 24:1 - Benoît Dupont de Dinechin:
Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus. 25:1
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-22 02:24 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
