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ORCID27th NATW 2018: Essex, VT, USA
- 27th IEEE North Atlantic Test Workshop, NATW 2018, Essex, VT, USA, May 7-9, 2018. IEEE 2018, ISBN 978-1-5386-6400-1
- Mehmet Ince, Ender Yilmaz, Sule Ozev:
Enabling fast process variation and fault simulation through macromodelling of analog components. 1-6 - Hui Jiang, Fanchen Zhang, Yi Sun, Jennifer Dworak:
One more time! Increasing fault detection with scan shift capture. 1-7 - Wei Jiang, Guoan Wang:
A simplified on-chip calibration method for branch-line coupler. 1-3 - Timothy M. Platt, Chen Liu:
Reducing test time with FPGA accelerators using OpenCL. 1-9 - Michael S. Shur, John Suarez:
Nanoscale silicon mosfet response to THz radiation for testing VLSI. 1-6 - Ryan Pennucci, Ryan Jurasek, Wolfgang Hokenmaier, Lester Patrick, Jacob Bucci, Donald Labrecque, David Kinney:
An analysis of an inexpensive memory test solution. 1-6 - Nabil El Belghiti Alaoui, Patrick Tounsi, Alexandre Boyer, Arnaud Viard:
New testing approach using near electromagnetic field probing intending to upgrade in-circuit testing of high density PCBAs. 1-8 - Imtiaz Ahmed, Subhash Baraiya, Rahul Singhal:
Case study on low pin count testing of industry transceiver chip. 1-5
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