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Masayuki Ikebe
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Publications
- 2022
- [j15]Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. 32(5): 2666-2686 (2022) - 2020
- [j12]Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai:
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3015-3028 (2020) - 2019
- [j11]Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. 102-D(12): 2295-2305 (2019) - [j10]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. 102-D(12): 2341-2353 (2019) - [c34]Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA 2019: 1-8 - 2018
- [j9]Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018: 3618621:1-3618621:11 (2018) - [j8]Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [j7]Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano:
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems 61: 21-31 (2018) - [c31]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT 2018: 6-13 - [c30]Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai:
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP 2018: 1842-1846 - [c29]Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC 2018: 237-243 - [c28]Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP 2018: 1-4 - 2017
- [c27]Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
Accelerating deep learning by binarized hardware. APSIPA 2017: 1045-1051 - [c26]Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura:
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC 2017: 7-8 - [c25]Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL 2017: 1 - [c24]Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
A Time-Division Multiplexing Ising Machine on FPGAs. HEART 2017: 3:1-3:6 - [c23]Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR 2017: 291-297 - [c22]Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN 2017: 2510-2516 - [c21]Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura:
Low latency divider using ensemble of moving average curves. ISQED 2017: 397-402 - [c20]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - [c19]Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. 2017: 137-142 - 2016
- [c18]Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS 2016: 297-300 - [c17]Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura:
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC 2016: 105-108 - [c15]Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig 2016: 1-6 - [c14]Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig 2016: 1-6 - 2015
- [c12]Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC 2015: 82- - 2013
- [c9]Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS 2013: 169-172 - 2005
- [j3]Masayuki Ikebe, Tetsuya Asai:
A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA. J. Robotics Mechatronics 17(4): 372-377 (2005) - [j2]Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya:
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005) - 2004
- [j1]Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya:
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. 19(4) (2004)
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