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ORCIDMohamed Zahran 0001
Person information
- affiliation: New York University, Computer Science Department, NY, USA
Other persons with the same name
- Mohamed Zahran — disambiguation page
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2020 – today
- 2023
[j12]Dina Tantawy
, Mohamed Zahran, Amr G. Wassal:
PTcomp: Post-Training Compression Technique for Generative Adversarial Networks. IEEE Access 11: 9763-9774 (2023)- 2022
- [c18]Marcelo Pias, Brett A. Becker, Qiao Xiang, Mohamed Zahran, Monica Anderson:
Should Quantum Processor Design be Considered a Topic in Computer Architecture Education? SIGCSE (2) 2022: 1184 - [e1]Valentina Salapura, Mohamed Zahran, Fred Chong, Lingjia Tang:
ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18 - 22, 2022. ACM 2022, ISBN 978-1-4503-8610-4 [contents] - 2021
- [i1]Dina Tantawy, Mohamed Zahran, Amr Wassal:
A Survey on GAN Acceleration Using Memory Compression Technique. CoRR abs/2108.06626 (2021)
2010 – 2019
- 2019
- [j11]Mahmoud Khairy, Amr G. Wassal, Mohamed Zahran:
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity. J. Parallel Distributed Comput. 127: 65-88 (2019) - [c17]Antonio Mallia, Michal Siedlaczek, Torsten Suel, Mohamed Zahran:
GPU-Accelerated Decoding of Integer Lists. CIKM 2019: 2193-2196 - [c16]Mohamed Zahran, Marsha J. Berger:
Parallel Computing At The Undergraduate Level: Lessons Learned and Insights. WCAE@ISCA 2019: 9:1-9:7 - 2017
- [j10]Mohamed Zahran:
Heterogeneous computing: here to stay. Commun. ACM 60(3): 42-45 (2017) - [j9]Mahmoud Khairy, Mohamed Zahran, Amr G. Wassal:
SACAT: Streaming-Aware Conflict-Avoiding Thrashing-Resistant GPGPU Cache Management Scheme. IEEE Trans. Parallel Distributed Syst. 28(6): 1740-1753 (2017) - [c15]Chris Rohlfs, Mohamed Zahran:
Optimal Bandwidth Selection for Kernel Regression Using a Fast Grid Search and a GPU. IPDPS Workshops 2017: 550-556 - [c14]Numair Khan, Mohamed Zahran:
Space-Efficient Pointwise Computation of the Distance Transform on GPUs. IPDPS Workshops 2017: 557-566 - 2016
- [j8]Mohamed Zahran:
Heterogeneous Computing: Here to Stay. ACM Queue 14(6): 31-42 (2016) - 2015
- [c13]Mahmoud Khairy, Mohamed Zahran, Amr G. Wassal:
Efficient utilization of GPGPU cache hierarchy. GPGPU@PPoPP 2015: 36-47 - 2013
- [j7]Jeyavijayan Rajendran, Arun K. Kanuparthi, Mohamed Zahran, Sateesh Addepalli, Gaston Ormazabal, Ramesh Karri:
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. IEEE Des. Test 30(2): 35-44 (2013) - 2012
- [j6]Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri:
Architecture Support for Dynamic Integrity Checking. IEEE Trans. Inf. Forensics Secur. 7(1): 321-332 (2012) - 2011
- [c12]Corey Malone, Mohamed Zahran, Ramesh Karri:
Are hardware performance counters a cost effective way for integrity checking of programs. STC@CCS 2011: 71-76 - [c11]Artem Durytskyy, Mohamed Zahran, Ramesh Karri:
Improving GPU Robustness by making use of faulty parts. ICCD 2011: 346-351 - 2010
- [j5]Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran:
On-chip sensor-driven efficient thermal profile estimation algorithms. ACM Trans. Design Autom. Electr. Syst. 15(3): 25:1-25:27 (2010) - [j4]Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed I. Elmasry:
On the Power Management of Simultaneous Multithreading Processors. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1243-1248 (2010) - [c10]Mohamed Zahran, Sally A. McKee:
Global management of cache hierarchies. Conf. Computing Frontiers 2010: 131-140 - [c9]Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri:
Feasibility study of dynamic Trusted Platform Module. ICCD 2010: 350-355
2000 – 2009
- 2009
- [j3]Kim M. Hazelwood, Mohamed Zahran:
Challenges and opportunities at all levels: interactions among operating systems, compilers, and multicore processors. ACM SIGOPS Oper. Syst. Rev. 43(2): 3-4 (2009) - 2008
- [c8]Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran:
Chip level thermal profile estimation using on-chip temperature sensors. ICCD 2008: 432-437 - 2007
- [j2]Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj Franklin:
Non-Inclusion Property in Multi-Level Caches Revisited. Int. J. Comput. Their Appl. 14(2): 99-108 (2007) - 2006
- [c7]Mohamed M. Zahran, Manoj Franklin:
RHT: A Context-Based Return Address Predictor. CDES 2006: 17-23 - [c6]Anasua Bhowmik, Mohamed M. Zahran:
Bandwidth-Friendly Cache Hierarchy. CDES 2006: 153-159 - 2005
- [c5]Mohamed M. Zahran, Anasua Bhowmik:
Hybrid compiler and microarchitecture technique for cache traffic optimization. Interaction between Compilers and Computer Architectures 2005: 58-69 - 2004
- [c4]François Cantonnet, Yiyi Yao, Mohamed M. Zahran, Tarek A. El-Ghazawi:
Productivity Analysis of the UPC Language. IPDPS 2004 - 2003
- [j1]Mohamed M. Zahran:
On cache memory hierarchy for Chip-Multiprocessor. SIGARCH Comput. Archit. News 31(1): 39-48 (2003) - [c3]Mohamed M. Zahran, Manoj Franklin:
Dynamic Thread Resizing for Speculative Multithreaded Processors. ICCD 2003: 313- - 2002
- [c2]Mohamed M. Zahran, Manoj Franklin:
Return-Address Prediction in Speculative Multithreaded Environments. HiPC 2002: 609-619 - [c1]Mohamed M. Zahran, Manoj Franklin:
A Feasibility Study of Hierarchical Multithreading. IPDPS 2002
Coauthor Index
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