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ORCID30th VLSI Design 2017: Hyderabad, India
- 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017. IEEE Computer Society 2017, ISBN 978-1-5090-5740-5
Session A1: Analog, Mixed Signal and RF Design I
- Sudipta Sarkar, Yongda Cai, Anubhav Adak:
Two-Step Residue Transfer Technique for High-Speed Pipeline A/Ds. 3-8 - Ashwin Kumar Siva Kumar, Debasish Behera, Nagendra Krishnapura
:
A Low Power Multi-channel Input Delta-Sigma ADC without Reset. 9-14 - Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects. 15-20 - Javed S. Gaggatur, Immanuel Raja, Gaurab Banerjee:
On-Chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power Amplifier. 21-26
Session B1: Caches and Memory
- Sukarn Agarwal, Hemangee K. Kapoor:
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. 29-34 - Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. 35-40 - Ishan G. Thakkar, Sudeep Pasricha:
DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. 41-46 - Jiayin Li, Kartik Mohanram:
Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies. 47-52
Session C1: FPGA and Reconfigurable Systems
- Bibin Johnson, Nimin Thomas, J. Sheeba Rani:
An FPGA Based High throughput Discrete Kalman Filter Architecture for Real-Time Image Denoising. 55-60 - Sangeetha Damotharasamy, P. Deepa:
Efficient Scale Invariant Human Detection Using Histogram of Oriented Gradients for IoT Services. 61-66 - Manideepa Mukherjee, Alexander Fell, Apala Guha:
DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures. 67-72
Session D1: Low Power I
- Shounak Chakraborty, Hemangee K. Kapoor:
Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors. 75-80 - Anand Savanth, Alex S. Weddell, James Myers, David Flynn, Bashir M. Al-Hashimi:
A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems. 81-86 - Hemanta Kumar Mondal, Shashwat Kaushik, Sri Harsha Gade, Sujay Deb:
Energy-Efficient Transceiver for Wireless NoC. 87-92
Session A2: Low Power II
- Sumit Naikwad, Murali Krishna Rajendran, Priya Sunil, Ashudeb Dutta:
A Single Inductor, Single Input Dual Output (SIDO) Piezoelectric Energy Harvesting System. 95-100 - Saransh Sharma, Avilash Mukherjee, Abhishek Dongre, Mrigank Sharad:
Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design. 101-106 - Sukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi:
Markov Chain Model Using Lévy Flight for VLSI Power Grid Analysis. 107-112
Session B2: VLSI Architectures
- Bidesh Chakraborty, Mamata Dalui, Biplab K. Sikdar:
Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols. 115-120 - M. Mohamed Asan Basiri, Sk. Noor Mahammad:
High Performance Integer DCT Architectures for HEVC. 121-126 - Mohd. Tasleem Khan, Shaik Rafi Ahamed, Forrest Brewer:
Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic. 127-132
Session C2: Test, Reliability and Fault Tolerance I
- Pascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker:
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model. 135-140 - Prasenjit Biswas, D. M. H. Walker:
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 141-146 - Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita:
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. 147-152
Session D2: Security I
- Fatemeh Tehranipoor, Nima Karimian, Wei Yan, John A. Chandy:
A Study of Power Supply Variation as a Source of Random Noise. 155-160 - N. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya:
Compact Implementations of FPGA-based PUFs with Enhanced Performance. 161-166 - Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran:
NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. 167-172
Session A3: Analog, Mixed Signal and RF Design II
- Abhishek Srivastava, Nithin Sankar, Devarshi Das, Maryam Shojaei Baghini:
LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare Applications. 175-180 - Deepak Joshi, Satyabrata Dash, Ayush Malhotra, Pulimi Venkata Sai, Rahul Das, Dikshit Sharma, Gaurav Trivedi:
Optimization of 2.4 GHz CMOS Low Noise Amplifier Using Hybrid Particle Swarm Optimization with Lévy Flight. 181-186 - Sanjeev Nyshadham, A. G. Krishna Kanth:
A 6V to 42V High Voltage CMOS Bandgap Reference Robust to RF Interference for Automotive Applications. 187-192 - Mahesh Zanwar, Subhajit Sen:
Programmable Output Multi-phase Switched Capacitor Step-Up DC-DC Converter with SAR-based Regulation. 193-198
Session B3: Embedded Systems
- Javed S. Gaggatur, Gaurab Banerjee:
High Gain Capacitance Sensor Interface for the Monitoring of Cell Volume Growth. 201-206 - Kajal Varma, Geeta Patil, Biju K. Raveendran:
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. 207-212 - Rajesh Kedia, K. K. Yoosuf, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, M. Balakrishnan:
MAVI: An Embedded Device to Assist Mobility of Visually Impaired. 213-218 - Anshuman Tripathi, Arnab Sarkar, P. P. Chakrabarti:
Migration Aware Low Overhead ERfair Scheduler. 219-224
Session C3: Formal Techniques in Design
- Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Dynamic Power Optimization Based on Formal Property Checking of Operations. 227-232 - Antonio Anastasio Bruto da Costa, Pallab Dasgupta:
Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy. 233-238 - Sudipa Mandal, Antonio Anastasio Bruto da Costa, Aritra Hazra, Pallab Dasgupta, Bhushan Naware, Chunduri Rama Mohan, Sanjib Basu:
Formal Verification of Power Management Logic with Mixed-Signal Domains. 239-244 - Antara Ain, Akshay Mambakam, Pallab Dasgupta, Siddhartha Mukhopadhyay:
Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs. 245-250
Session A4: Analog, Mixed Signal and RF Design III
- R. R. Manikandan, Venkata Narayana Rao Vanukuru:
A High Performance Switchable Multiband Inductor Structure for LC-VCOs. 253-258 - Sanjay Kumar Wadhwa, Nidhi Chaudhry:
High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet. 259-262 - Vinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav:
A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET. 269-274
Session B4: Emerging Technologies I
- Debjyoti Bhattacharjee, Anupam Chattopadhyay:
Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays. 277-282 - Y. V. Bhuvaneshwari, Abhinav Kranti:
Extraction and Analysis of Mobility in Double Gate Junctionless Transistor. 283-288 - Abhoy Kole, Kamalika Datta:
Improved NCV Gate Realization of Arbitrary Size Toffoli Gates. 289-294 - Vipul Kumar Mishra, Himanshu Thapliyal:
Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies. 295-300
Session C4: Digital Circuits
- Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra:
A 64b/66b Line Encoding for High Speed Serializers. 303-308 - Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari:
Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology. 309-314 - Poorvi Jain, Bishnu Prasad Das:
Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator. 315-320 - Mahadev Govind Shirwaikar, Naveen Kadayinti, Dinesh Kumar Sharma:
Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter. 321-326
Session A5: Analog, Mixed Signal and RF Design IV
- Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas:
A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. 329-334 - Bhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma:
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. 335-340 - Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat:
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. 341-346 - Mohammed Umar Shaikh, Sivaramakrishna Rudrapati, Nandish Bharat Thaker, Shalabh Gupta:
Frequency Enhancement in Miller Divider with Injection-Locking Portrait. 347-352
Session B5: Emerging Technologies II
- Sarit Chakraborty, Susanta Chakraborty:
A Novel Approach towards Biochemical Synthesis on Cyberphysical Digital Microfluidic Biochip. 355-360 - Bhawani Shankar, Ankit Soni, Manikant Singh, Rohith Soman, K. N. Bhat, Srinivasan Raghavan, Navakanta Bhat, Mayank Shrivastava:
ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis. 361-365 - Madhav Rao:
Electrical Modeling and Characterization of Copper/Carbon Nanotubes in Tapered through Silicon Vias. 366-371 - Debasri Saha, Susmita Sur-Kolay:
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs. 372-377
Session C5: CMOS Technologies I
- Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan:
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs. 381-384 - Rajat Vishnoi, Pratyush Panday, Mamidala Jagadesh Kumar:
DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions. 385-390 - Milova Paul, Christian Russ, Boeila Sampath Kumar, Harald Gossner, Mayank Shrivastava:
Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete? 391-394
Session A6: Test, Reliability and Fault Tolerance II
- Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh:
On Testing of Superscalar Processors in Functional Mode for Delay Faults. 397-402 - Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee:
Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware. 403-408 - Sparsh Mittal, Haonan Wang, Adwait Jog, Jeffrey S. Vetter:
Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File. 409-414
Session B6: Security II
- Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at Runtime. 417-422 - K. B. Anuroop, Anu James, M. Neema:
Hardware Software Codesign for a Hybrid Substitution Box. 423-428 - Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta:
A New Logic Encryption Strategy Ensuring Key Interdependency. 429-434
Session C6: CMOS Technologies II
- Adil Meersha, B. Sathyajit, Mayank Shrivastava:
A Systematic Study on the Hysteresis Behaviour and Reliability of MoS2 FET. 437-440 - Manish Gupta, Abhinav Kranti:
Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs. 441-446 - Pardeep Kumar, S. Srivatsa, P. Mantripragada, S. Upreti, K. V. Shravya:
Hybrid OPC Technique for Fast and Accurate Lithography Simulation. 447-450
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