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Publication search results
found 113 matches
- 2014
- Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC 2014: 211-214 - Shahbaz Abbasi, Ayman Shabra:
1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS. ESSCIRC 2014: 355-358 - Mohammed Abdulaziz, Markus Törmänen, Henrik Sjöland:
A 4th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOS. ESSCIRC 2014: 367-370 - Marko Aleksic:
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS. ESSCIRC 2014: 451-454 - Abdelali El Amraoui, Marc Bocquet, F. Barros, Jean-Michel Portal, M. Charbonneau, Stéphanie Jacob, Jacqueline Bablet, Mohamed Benwadih, Vincent Fischer, Romain Coppard, R. Gwoziecky:
Printed complementary organic thin film transistors based decoder for ferroelectric memory. ESSCIRC 2014: 111-114 - Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues:
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. ESSCIRC 2014: 243-246 - Greg Atwood, Scott DeBoer, Kirk Prall, Linda Somerville:
A semiconductor memory development and manufacturing perspective. ESSCIRC 2014: 1-6 - Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450 - Aritra Banerjee, Rahmi Hezar, Lei Ding, Nathan Schemm, Baher Haroun:
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS. ESSCIRC 2014: 467-470 - Pinar Basak Basyurt, Devrim Yilmaz Aksin, Edoardo Bonizzoni, Franco Maloberti:
A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage reference. ESSCIRC 2014: 115-118 - Debasish Behera, Nagendra Krishnapura:
A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter. ESSCIRC 2014: 415-418 - Ulrich Bihr, Jens Anders, J. Rickert, Martin Schuettler, A. Moeller, K. H. Boven, Joachim Becker, Maurits Ortmanns:
A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance. ESSCIRC 2014: 103-106 - Vincent Binet, Francois Amiard, Emmanuel Allier, Simon Valcin, Angelo Nagari:
A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing. ESSCIRC 2014: 319-322 - Avishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan:
A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency. ESSCIRC 2014: 271-274 - Assim Boukhayma, Jean-Pierre Rostaing, A. Mollard, Fabrice Guellec, Michele Benetti, Guillaume Ducournau, Jean-François Lampin, Antoine Dupret, Christian C. Enz, Michaël Tchagaspanian, J.-A. Nicolas:
A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation. ESSCIRC 2014: 303-306 - Paolo Bruschi, F. Del Cesta, Aurelio Nunzio Longhitano, Massimo Piotto, Roberto Simmarano:
A very compact CMOS instrumentation amplifier with nearly rail-to-rail input common mode range. ESSCIRC 2014: 323-326 - Carl Bryant, Henrik Sjöland:
A 2.45GHz, 50uW wake-up receiver front-end with -88dBm sensitivity and 250kbps data rate. ESSCIRC 2014: 235-238 - Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, Chung-Chih Hung, Chin-Long Wey, Hsin-Yu Luo:
Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology. ESSCIRC 2014: 167-170 - Shin-Hao Chen, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Sheng Kang, Kevin Cheng, Li-Ren Huang, Chao-Jen Huang, Hsin-Yu Luo:
A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique. ESSCIRC 2014: 315-318 - Long Chen, Arindam Sanyal, Ji Ma, Nan Sun:
A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. ESSCIRC 2014: 219-222 - Myungjoon Choi, Inhee Lee, Tae-Kwang Jang, David T. Blaauw, Dennis Sylvester:
A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs. ESSCIRC 2014: 119-122 - Abhishek Chowdhary, Alok Kaushik, Sajal Kumar Mandal, Sanjeev Chopra, Tapas Nandy, Vivek Uppal:
A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst. ESSCIRC 2014: 443-446 - Peng Cong, Piyush Karande, Jonathan Landes, Rob Corey, Scott Stanslaski, Wesley Santa, Randy Jensen, Forrest Pape, Dan Moran, Tim Denison:
A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operation. ESSCIRC 2014: 99-102 - Hooman Darabi, David Murphy, Mohyee Mikhemar, Ahmad Mirzaei:
Blocker tolerant software defined receivers. ESSCIRC 2014: 35-42 - Gabriele Devita, Alan Chi Wai Wong, Mark Dawkins, Kostas N. Glaros, U. Kiani, Franco Lauria, V. Madaka, Okundu C. Omeni, Johannes Schiff, A. Vasudevan, L. Whitaker, S. Yu, Alison J. Burdett:
A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications. ESSCIRC 2014: 283-286 - Michele Dini, Matteo Filippi, Aldo Romani, Marco Tartagni, Valeria Bottarel, Giulio Ricotti:
A 40 nA/source energy harvesting power converter for multiple and heterogeneous sources. ESSCIRC 2014: 259-262 - Mikko Englund, Kim B. Ostman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Jussi Ryynänen, Kimmo Koli:
A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator. ESSCIRC 2014: 371-374 - Luca Fanori, Thomas Mattsson, Pietro Andreani:
A Class-D CMOS DCO with an on-chip LDO. ESSCIRC 2014: 335-338 - Ali Fekri, Mohammad Reza Nabavi, Nikola Radeljic-Jakic, Zu-yao Chang, Michiel A. P. Pertijs, Stoyan N. Nihtianov:
An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADC. ESSCIRC 2014: 403-406 - Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel:
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC 2014: 435-438
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