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Publication search results
found 57 matches
- 2007
- Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu:
Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234 - Waleed K. Al-Assadi, Sindhu Kakarla:
Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design. DFT 2007: 215-222 - Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi:
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. DFT 2007: 21-30 - Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Sandro Pastore, Giacomo R. Sechi, Roland Weigand:
Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform. DFT 2007: 105-113 - Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan:
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. DFT 2007: 340-348 - Hossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti:
Estimating Error Propagation Probabilities with Bounded Variances. DFT 2007: 41-49 - Swapnil Bahl:
A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema. DFT 2007: 331-339 - Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto:
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. DFT 2007: 132-141 - Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani:
A Functional Verification Based Fault Injection Environment. DFT 2007: 114-122 - Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio:
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. DFT 2007: 87-95 - Ravi Bonam, Yong-Bin Kim, Minsu Choi:
Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. DFT 2007: 161-169 - Yoon-Hwa Choi, Myeong-Hyeon Lee:
A Defect-Tolerant Molecular-Based Memory Architecture. DFT 2007: 143-151 - Abderrahim Doumar, Kentaroh Katoh, Hideo Ito:
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40 - Jozsef Dudas, Michelle L. La Haye, Jenny Leung, Glenn H. Chapman:
A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects. DFT 2007: 517-525 - Avijit Dutta, Nur A. Touba:
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. DFT 2007: 3-11 - Timothy J. Dysart, Peter M. Kogge:
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder. DFT 2007: 478-486 - Michele Favalli:
Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth. DFT 2007: 170-178 - Michele Favalli, Marcello Dalpasso:
High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations. DFT 2007: 448-456 - Laura Frigerio, Fabio Salice:
RAM-Based Fault Tolerant State Machines for FPGAs. DFT 2007: 312-320 - Masaru Fukushi, Susumu Horiguchi, Luke Demoracski, Fabrizio Lombardi:
A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks. DFT 2007: 391-399 - Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena:
SET Emulation Under a Quantized Delay Model. DFT 2007: 68-77 - Rani S. Ghaida, Payman Zarkesh-Ha:
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. DFT 2007: 59-67 - Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Safety Evaluation of NanoFabrics. DFT 2007: 418-426 - Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi:
Error Tolerance of DNA Self-Healing Assemblies by Puncturing. DFT 2007: 400-408 - Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube:
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. DFT 2007: 50-58 - Jing Huang, Xiaojun Ma, Cecilia Metra, Fabrizio Lombardi:
Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. DFT 2007: 469-477 - Takashi Ikeda, Kazuteru Namba, Hideo Ito:
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290 - Abhijit Jas, Srinivas Patil:
Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT 2007: 252-260 - Mandar V. Joshi, Waleed Al-Assadi:
Nanofabric PLA architecture with Redundancy Enhancement. DFT 2007: 427-435 - Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi:
Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs. DFT 2007: 179-187
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