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Publication search results
found 110 matches
- 2005
- Salem Abdennadher, Saghir A. Shaikh:
Practices in Testing of Mixed-Signal and RF SoCs. Asian Test Symposium 2005: 467 - Salem Abdennadher, Saghir A. Shaikh:
Challenges in High Speed Interface Testing. Asian Test Symposium 2005: 468 - Vishwani D. Agrawal, Alok S. Doshi:
Concurrent Test Generation. Asian Test Symposium 2005: 294-299 - Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath:
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439 - Varun Arora, Indranil Sengupta:
A Unified Approach to Partial Scan Design using Genetic Algorithm. Asian Test Symposium 2005: 414-421 - Dong Hyun Baik, Kewal K. Saluja:
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. Asian Test Symposium 2005: 272-277 - Kedarnath J. Balakrishnan:
Emerging Techniques for Test Data Compression. Asian Test Symposium 2005: 462 - Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil:
Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433 - K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil:
A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. Asian Test Symposium 2005: 40-45 - Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar:
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. Asian Test Symposium 2005: 88-93 - Tapan J. Chakraborty:
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. Asian Test Symposium 2005: 464-465 - Sreejit Chakravarty:
Improving Logic Test Quality of Microprocessors. Asian Test Symposium 2005 - R. Chandramouli:
Managing Test and Repair of Embedded Memory Subsystem in SoC. Asian Test Symposium 2005: 452 - Sasikumar Cherubal:
Challenges in Next Generation Mixed-Signal IC Production Testing. Asian Test Symposium 2005: 466 - Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman:
Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470 - Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic. Asian Test Symposium 2005: 260-265 - Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar:
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. Asian Test Symposium 2005: 284-287 - Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175 - Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen:
Flash Memory Die Sort by a Sample Classification Method. Asian Test Symposium 2005: 182-187 - V. R. Devanathan:
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. Asian Test Symposium 2005: 300-305 - Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium 2005: 202-207 - Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait:
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. Asian Test Symposium 2005: 378-385 - Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
Partial Gating Optimization for Power Reduction During Test Application. Asian Test Symposium 2005: 242-247 - Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi:
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241 - Yu-Hsuan Fu, Sying-Jyan Wang:
Test Data Compression with Partial LFSR-Reseeding. Asian Test Symposium 2005: 343-347 - Indradeep Ghosh:
High Level Test Generation for Custom Hardware: An Industrial Perspective. Asian Test Symposium 2005: 458 - Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409 - Sameer Goel, Rubin A. Parekhji:
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. Asian Test Symposium 2005: 330-336 - Shalabh Goyal, Michael Purtell:
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester. Asian Test Symposium 2005: 14-17 - Guangmei Zhang, Chen Rui, Xiaowei Li, Congying Han:
The Automatic Generation of Basis Set of Path for Path Testing. Asian Test Symposium 2005: 46-51
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