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Publication search results
found 42 matches
- 2006
- Yogindra Abhyankar, C. Sajish, Yogesh Agarwal, C. R. Subrahmanya, Peeyush Prasad:
High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform. ReConFig 2006: 328-331 - Marcos R. de Alba-Rosano, Andrés David García García:
Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells. ReConFig 2006: 149-155 - Nilton B. Armstrong, Heitor S. Lopes
, Carlos Raimundo Erig Lima
:
Preliminary Steps Towards Protein Folding Prediction Using Reconfigurable Computing. ReConFig 2006: 92-98 - Steven Bishop, Suresh Rai, Bahadir K. Gunturk
, Jerry L. Trahan
, Ramachandran Vaidyanathan:
Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image Compression. ReConFig 2006: 208-216 - Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer:
A Reconfigurable Simulation Framework for Financial Computation. ReConFig 2006: 30-38 - Javier Castillo, Pablo Huerta, César Pedraza, José Ignacio Martínez:
A Self-Reconfigurable Multimedia Player on FPGA. ReConFig 2006: 6-11 - Sumanta Chaudhuri
, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst:
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig 2006: 47-55 - Ameet Chavan, Gaurav Dukle, Ben Graniello, Eric W. MacDonald
:
Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures. ReConFig 2006: 142-148 - Andres Cicuttin, Maria Liz Crespo
, Alexander Shapiro, Nizar Abdallah:
A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology. ReConFig 2006: 39-46 - Florian Dittmann, Achim Rettberg, Raphael Weber:
Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. ReConFig 2006: 262-269 - Ahmed Elhossini, Shawki Areibi, Robert D. Dony:
An FPGA Implementation of the LMS Adaptive Filter for Audio Processing. ReConFig 2006: 168-175 - Julio A. de Oliveira Filho, Thomas Schweizer, Tobias Oppold, Tommy Kuhn, Wolfgang Rosenstiel:
Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain. ReConFig 2006: 71-77 - Marcelo Götz
, Florian Dittmann:
Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time Reconfiguration. ReConFig 2006: 12-19 - Elvira Martínez de Icaya, Victoria Rodellar, Coral Gonzalez-Concejero, Virginia Peinado, Vicente Angel García:
Design Space Exploration for an Adaptive Noise Cancellation Algorithm. ReConFig 2006: 184-190 - Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga:
Realization of the sound space environment for the radiation-tolerant space craft. ReConFig 2006: 198-205 - Maurice Keller, Robert Ronan, William P. Marnane
, Colin C. Murphy:
A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor. ReConFig 2006: 158-167 - Timothy Lantz, Eric Peskin:
A QCA Implementation of a Configurable Logic Block for an FPGA. ReConFig 2006: 132-141 - Santos López-Estrada, René Cumplido:
Decision Tree Based FPGA-Architecture for Texture Sea State Classification. ReConFig 2006: 191-197 - Gerardo Eli Martínez-Torres, J. M. Luna-Rivera
, Raul E. Balderas-Navarro:
FPGA-Based Educational Platform for Wireless Transmission Using System Generator. ReConFig 2006: 304-313 - José Martínez
, Leopoldo Altamirano Robles
:
FPGA-based Pipeline Architecture to Transform Cartesian Images into Foveal Images by Using a new Foveation Approach. ReConFig 2006: 227-236 - Ulises S. Mendoza-Camarena, René de Jesús Romero-Troncoso:
VHDL Core for the Computation of the One-Dimensional Discrete Cosine Transform. ReConFig 2006: 332-339 - Miguel Morales-Sandoval
, Claudia Feregrino Uribe:
GF(2m) Arithmetic Modules for Elliptic Curve Cryptography. ReConFig 2006: 176-183 - Guilherme Luiz Moritz
, Cristiano Jory, Heitor S. Lopes
, Carlos Raimundo Erig Lima
:
Implementation of a Parallel Algorithm for Protein Pairwise Alignment Using Reconfigurable Computing. ReConFig 2006: 99-105 - Daniel M. Muñoz
, Carlos H. Llanos
, Mauricio Ayala-Rincón
, Rudi H. van Els
:
Implementation, Simulation and Validation of Dispatching Algorithms for Elevator Systems. ReConFig 2006: 290-297 - Rashad S. Oreifej, Carthik A. Sharma, Ronald F. DeMara
:
Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware. ReConFig 2006: 106-113 - Jorge Peña, Mauricio Vanegas
, Andrés Valencia:
Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring Function. ReConFig 2006: 114-121 - Julio C. G. Pimentel:
Implementation of Simulation Algorithms in FPGA for Real Time Simulation of Electrical Networks with Power Electronics Devices. ReConFig 2006: 320-327 - Omar Piña-Ramirez, Raquel Valdés-Cristerna, Oscar Yáñez-Suárez
:
An FPGA Implementation of Linear Kernel Support Vector Machines. ReConFig 2006: 314-319 - René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias, Arturo Garcia-Perez:
8-bit CISC Microprocessor Core for Teaching Applications in the Digital Systems Laboratory. ReConFig 2006: 300-303 - Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl:
Datapath and ISA Customization for Soft VLIW Processors. ReConFig 2006: 280-289
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retrieved on 2024-07-02 18:35 CEST from data curated by the dblp team
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