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Publication search results
found 43 matches
- 1992
- V. H. Allen, J. Janardhan, R. M. Lee, M. Srinivas:
Enhanced region scheduling on a program dependence graph. MICRO 1992: 72-80 - Steven J. Beaty:
Lookahead scheduling. MICRO 1992: 256-259 - Carl J. Beckmann, Constantine D. Polychronopoulos:
Microarchitecture support for dynamic scheduling of acyclic task graphs. MICRO 1992: 140-148 - David Bernstein, Doron Cohen, Yuval Lavon, Vladimir Rainish:
Performance evaluation of instruction scheduling on the IBM RISC System/6000. MICRO 1992: 226-235 - Brian K. Bray, Michael J. Flynn:
Translation hint buffers to reduce access time of physically-addressed instruction caches. MICRO 1992: 206-209 - Michael Butler, Yale N. Patt:
An investigation of the performance of various dynamic scheduling techniques. MICRO 1992: 1-9 - Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau:
Partitioned register files for VLIWs: a preliminary analysis of tradeoffs. MICRO 1992: 292-300 - Meng-chou Chang, Feipei Lai, Rung-Ji Shang:
Exploiting instruction-level parallelism with the conjugate register file scheme. MICRO 1992: 29-32 - William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo:
An efficient architecture for loop based data preloading. MICRO 1992: 92-101 - Chien-Ming Chen, Yunn Yen Chen, Chung-Ta King:
Branch merging for effective exploitation of instruction-level parallelism. MICRO 1992: 37-40 - Thomas M. Conte:
Tradeoffs in processor/memory interfaces for superscalar processors. MICRO 1992: 202-205 - Benoît Dupont de Dinechin:
StaCS: a Static Control Superscalar architecture. MICRO 1992: 282-291 - Harry Dwyer, Hwa C. Torng:
An out-of-order superscalar processor with speculative execution and fast, precise interrupts. MICRO 1992: 272-281 - Matthew K. Farrens, Arvin Park, Gary S. Tyson:
Modifying VM hardware to reduce address pin requirements. MICRO 1992: 210-213 - Manoj Franklin, Gurindar S. Sohi:
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. MICRO 1992: 236-245 - John W. C. Fu, Janak H. Patel, Bob L. Janssens:
Stride directed prefetching in scalar processors. MICRO 1992: 102-110 - Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri:
A non-deterministic scheduler for a software pipelining compiler. MICRO 1992: 41-44 - Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271 - Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh:
Performance analysis and design methodology for a scalable superscalar architecture. MICRO 1992: 246-255 - Tokuzo Kiyohara, John C. Gyllenhaal:
Code scheduling for VLIW/superscalar processors with limited register files. MICRO 1992: 197-201 - Michael J. Knieser, Christos A. Papachristou:
Y-Pipe: a conditional branching scheme without pipeline delays. MICRO 1992: 125-128 - Philip LeNir, Ramaswamy Govindarajan, Shashank S. Nemawarkar:
Exploiting instruction-level parallelism: the multithreaded approach. MICRO 1992: 189-192 - William L. Lynch, Brian K. Bray, Michael J. Flynn:
The effect of page allocation on caches. MICRO 1992: 222-225 - Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann:
Effective compiler support for predicated execution using the hyperblock. MICRO 1992: 45-54 - Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis:
Interlock collapsing ALU for increased instruction-level parallelism. MICRO 1992: 149-157 - Brian A. Malloy, Rajiv Gupta, Mary Lou Soffa:
A shape matching approach for scheduling fine-grained parallelism. MICRO 1992: 264-267 - Soo-Mook Moon, Kemal Ebcioglu:
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors. MICRO 1992: 55-71 - B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops. MICRO 1992: 158-169 - André Seznec, Karl Courtel:
Controlling and sequencing a heavily pipelined floating-point operator. MICRO 1992: 111-114 - Bogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib:
A VLIW architecture for optimal execution of branch-intensive loops. MICRO 1992: 119-124
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retrieved on 2024-05-27 20:41 CEST from data curated by the dblp team
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