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Publication search results
found 56 matches
- 2001
- Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey:
Performance Evaluation of Checksum-Based ABFT. DFT 2001: 461- - Seok-Bum Ko
, Tian Xia, Jien-Chung Lo:
Efficient Parity Prediction in FPGA. DFT 2001: 176-181 - Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi:
A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application. DFT 2001: 191-199 - Yves Audet, Glenn H. Chapman:
Design of a Self-Correcting Active Pixel Sensor. DFT 2001: 18- - Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. DFT 2001: 29-38 - Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Analog BIST Generator for ADC Testing. DFT 2001: 338-346 - Mykola Blyzniuk, Irena Kazymyra
:
Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library. DFT 2001: 375-383 - Cristiana Bolchini, Fabio Salice:
A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. DFT 2001: 170-175 - Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi:
Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays. DFT 2001: 161-169 - Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda
, Massimo Violante:
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258 - John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici:
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT 2001: 445-454 - John Marty Emmert, Jason A. Cheatham:
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . DFT 2001: 149- - Jayabrata Ghosh-Dastidar, Nur A. Touba:
Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. DFT 2001: 215-220 - Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil:
Comparison and Application of Different VHDL-Based Fault Injection Techniques. DFT 2001: 233-241 - Neil Harrison:
A Simple via Duplication Tool for Yield Enhancement. DFT 2001: 39-47 - Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey:
Fast Run-Time Fault Location in Dependable FPGA-Based Applications. DFT 2001: 206-214 - J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone:
Embedded Core Testing Using Broadcast Test Architecture. DFT 2001: 95-103 - Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui:
On Variable-Shift-Based Fault Compensation of Fuzzy Controllers. DFT 2001: 436-444 - Farzin Karimi, Fabrizio Lombardi:
Parallel Testing of Multi-port Static Random Access Memories for BIST. DFT 2001: 271-279 - Ramesh Karri
, Kaijie Wu, Piyush Mishra, Yongkook Kim:
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. DFT 2001: 427-435 - Amir Kazéminéjad, Eric Belhaire:
Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. DFT 2001: 308-313 - Eleftherios Kolonis, Michael Nicolaidis:
Fail-Safe Synchronization Circuit for Duplicated Systems. DFT 2001: 412-417 - Israel Koren, Zahava Koren, Glenn H. Chapman:
Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-Chip. DFT 2001: 3-10 - Parag K. Lala, Alvernon Walker:
On-Line Error Detectable Carry-Free Adder Design. DFT 2001: 66-71 - Paul Lee, Alfred Chen, Dilip Mathew:
A Speed-Dependent Approach for Delta IDDQ Implementation. DFT 2001: 280-286 - Régis Leveugle:
A Low-Cost Hardware Approach to Dependability Validation of Ips. DFT 2001: 242-249 - Régis Leveugle, R. Cercueil:
High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. DFT 2001: 84- - Xiaowei Li, Huawei Li, Yinghua Min:
Reducing Power Dissipation during At-Speed Test Application. DFT 2001: 116- - Hans A. R. Manhaeve, Stefaan Kerckenaere:
An On-Chip Detection Circuit for the Verification of IC Supply Connections. DFT 2001: 57-65 - Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin
:
Survivable Self-Checking Sequential Circuits. DFT 2001: 395-402
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retrieved on 2024-06-23 14:35 CEST from data curated by the dblp team
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