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Publication search results
found 1,477 matches
- 2024
- Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch:
SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay. ASAP 2024: 118-119 - Andreas Böttcher, Martin Kumm:
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs. ASAP 2024: 217-225 - Mohamed Bouaziz
, Suhaib A. Fahmy:
Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper). ASAP 2024: 204-205 - Yannick Braatz, Taha Soliman, Shubham Rai, Dennis Sebastian Rieber, Oliver Bringmann:
CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions. ASAP 2024: 8-16 - Tao Cai, Jianfei Dai, Dejiao Niu, Lei Li, Zeyu Huang, Qiangqiang Ni:
A LLC-Friendly LSM-tree. ASAP 2024: 243-244 - Yasong Cao, Mei Wen, Junzhong Shen, Zhongxing Li:
BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM. ASAP 2024: 36-44 - Songqiao Cui, Josep Balasch:
Configurable Loop Shuffling via Instruction Set Extensions. ASAP 2024: 45-53 - Paul Delestrac, Jonathan Miquel, Debjyoti Bhattacharjee, Diksha Moolchandani, Francky Catthoor, Lionel Torres, David Novo:
Analyzing GPU Energy Consumption in Data Movement and Storage. ASAP 2024: 143-151 - Yude Fang, Junhui Wang, Libo Huang, Yongwen Wang, Weixia Xu:
Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor. ASAP 2024: 116-117 - Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez:
CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing. ASAP 2024: 228-236 - Yuchen Gui, Qizhe Wu, Wei Yuan, Huawen Liang, Xiaotian Wang, Xi Jin:
A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling. ASAP 2024: 77-78 - Annina Gutermann, Jürgen Becker:
A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper). ASAP 2024: 226-227 - Junzhe Huang, Qiang Dou, Li Shen:
Extending the RISC-V Instruction Set for High Performance Data Compression Hardware Acceleration. ASAP 2024: 131-132 - Valentin Isaac-Chassande, Adrian Evans, Yves Durand, Frédéric Rousseau:
SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix Kernels. ASAP 2024: 3-7 - Jens Karrenbauer, Sven Schönewald, Simon C. Klein, Holger Blume:
Enhancing a Hearing Aid Processor with ISA Extensions Supporting Flexible Fixed-Point Formats. ASAP 2024: 176-183 - Frederik Kautz, Sven Gesper, Gia Bao Thieu, Hans-Martin Blüthgen, Holger Blume, Guillermo Payá Vayá:
Multi-Level Prototyping of a Vertical Vector AI Processing System. ASAP 2024: 1-2 - Salim Khemira, Xinyuan Wang, Anh Nguyen, Yutaka Tamiya, Makoto Taiji, Takahide Yoshikawa, Jason Helge Anderson:
Raising Compute Density of Molecular Dynamics Simulation Through Approximate Memoization. ASAP 2024: 195-203 - Uyong Lee, Yeji Park, Junsu Heo, Sungkyung Park, Chester Sungchung Park:
Design Space Exploration of FFT Accelerators for IEEE 802.11ax using High-Level Synthesis. ASAP 2024: 120-121 - Jiangnan Li, Yazhou Yan, Guowei Zhu, Wenbo Yin, Lingli Wang:
An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs. ASAP 2024: 17-18 - Yiyang Lin, Yi Zou, Yanfeng Yang:
CSIFA: A Configurable SRAM-based In-Memory FFT Accelerator. ASAP 2024: 161-162 - Yao Liu, Shiyang Chen, Long Ma, Guolong Yang, Kun Wan:
Real-Time Order Book Building and Snapshot Generating for High Frequency Trading on FPGA. ASAP 2024: 71-76 - Hanqing Liu, Xiaole Cui, Sunrui Zhang, Mingqi Yin, Yuanyuan Jiang, Xiaoxin Cui:
A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. ASAP 2024: 163-171 - Shengbai Luo, Bo Wang, Yihao Shi, Xueyi Zhang, Qingshan Xue, Sheng Ma:
Sparm: A Sparse Matrix Multiplication Accelerator Supporting Multiple Dataflows. ASAP 2024: 122-130 - Yingchang Mao, Qiang Liu, Ray C. C. Cheung:
MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training. ASAP 2024: 34-35 - Shinya Miura, Qiong Chang, Jun Miyazaki:
$k$-Way In-Place Merge by CPU-GPU Cooperative Processing. ASAP 2024: 152-160 - Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini:
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. ASAP 2024: 172-173 - Zhuoheng Ran, Muhammad A. A. Abdelgawad, Zekai Zhang, Ray C. C. Cheung, Hong Yan:
RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications. ASAP 2024: 135-142 - Oliver Renke, Christoph Riggers, Jens Karrenbauer, Holger Blume:
Design Space Exploration of Semantic Segmentation CNN SalsaNext for Constrained Architectures. ASAP 2024: 28-29 - Georg Rutishauser, Joan Mihali, Moritz Scherer, Luca Bonini:
xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems. ASAP 2024: 206-213 - Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe:
Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI. ASAP 2024: 239-240
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