- Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita:
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID 2017: 147-152 - Vinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav:
A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET. VLSID 2017: 269-274 - Pardeep Kumar, S. Srivatsa, P. Mantripragada, S. Upreti, K. V. Shravya:
Hybrid OPC Technique for Fast and Accurate Lithography Simulation. VLSID 2017: 447-450 - Jiayin Li, Kartik Mohanram:
Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies. VLSID 2017: 47-52 - Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari:
Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology. VLSID 2017: 309-314 - Sudipa Mandal, Antonio Anastasio Bruto da Costa, Aritra Hazra, Pallab Dasgupta, Bhushan Naware, Chunduri Rama Mohan, Sanjib Basu:
Formal Verification of Power Management Logic with Mixed-Signal Domains. VLSID 2017: 239-244 - R. R. Manikandan, Venkata Narayana Rao Vanukuru:
A High Performance Switchable Multiband Inductor Structure for LC-VCOs. VLSID 2017: 253-258 - Adil Meersha, B. Sathyajit, Mayank Shrivastava:
A Systematic Study on the Hysteresis Behaviour and Reliability of MoS2 FET. VLSID 2017: 437-440 - Vipul Kumar Mishra, Himanshu Thapliyal:
Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies. VLSID 2017: 295-300 - Sparsh Mittal, Haonan Wang, Adwait Jog, Jeffrey S. Vetter:
Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File. VLSID 2017: 409-414 - Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra:
A 64b/66b Line Encoding for High Speed Serializers. VLSID 2017: 303-308 - Hemanta Kumar Mondal, Shashwat Kaushik, Sri Harsha Gade, Sujay Deb:
Energy-Efficient Transceiver for Wireless NoC. VLSID 2017: 87-92 - Manideepa Mukherjee, Alexander Fell, Apala Guha:
DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures. VLSID 2017: 67-72 - Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee:
Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware. VLSID 2017: 403-408 - Sumit Naikwad, Murali Krishna Rajendran, Priya Sunil, Ashudeb Dutta:
A Single Inductor, Single Input Dual Output (SIDO) Piezoelectric Energy Harvesting System. VLSID 2017: 95-100 - Sanjeev Nyshadham, A. G. Krishna Kanth:
A 6V to 42V High Voltage CMOS Bandgap Reference Robust to RF Interference for Automotive Applications. VLSID 2017: 187-192 - Milova Paul, Christian Russ, Boeila Sampath Kumar, Harald Gossner, Mayank Shrivastava:
Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete? VLSID 2017: 391-394 - Pascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker:
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model. VLSID 2017: 135-140 - Madhav Rao:
Electrical Modeling and Characterization of Copper/Carbon Nanotubes in Tapered through Silicon Vias. VLSID 2017: 366-371 - Bhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma:
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSID 2017: 335-340 - Debasri Saha, Susmita Sur-Kolay:
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs. VLSID 2017: 372-377 - Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. VLSID 2017: 35-40 - Sangeetha Damotharasamy, P. Deepa:
Efficient Scale Invariant Human Detection Using Histogram of Oriented Gradients for IoT Services. VLSID 2017: 61-66 - Sudipta Sarkar, Yongda Cai, Anubhav Adak:
Two-Step Residue Transfer Technique for High-Speed Pipeline A/Ds. VLSID 2017: 3-8 - Anand Savanth, Alex S. Weddell, James Myers, David Flynn, Bashir M. Al-Hashimi:
A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems. VLSID 2017: 81-86 - Mohammed Umar Shaikh, Sivaramakrishna Rudrapati, Nandish Bharat Thaker, Shalabh Gupta:
Frequency Enhancement in Miller Divider with Injection-Locking Portrait. VLSID 2017: 347-352 - Saransh Sharma, Avilash Mukherjee, Abhishek Dongre, Mrigank Sharad:
Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design. VLSID 2017: 101-106 - Mahadev Govind Shirwaikar, Naveen Kadayinti, Dinesh Kumar Sharma:
Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter. VLSID 2017: 321-326 - Abhishek Srivastava, Nithin Sankar, Devarshi Das, Maryam Shojaei Baghini:
LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare Applications. VLSID 2017: 175-180