- René Krenz, Elena Dubrova, Andreas Kuehlmann:
Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions. IWLS 2002: 321-326 - Prabhakar Kudva, Andrew Sullivan, William E. Dougherty:
Metrics for Structural Logic Synthesis. IWLS 2002: 1-6 - Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan:
A LUT based Approach for High Level Synthesis on FPGAs. IWLS 2002: 167-172 - Steven P. Levitan:
Giga = 1/Nano: CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-Systems. IWLS 2002: 399 - Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev:
Visualization of Coding Conflicts in Asynchronous Circuit Design. IWLS 2002: 155-160 - Theodore W. Manikas, Gerald R. Kane:
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement. IWLS 2002: 27-30 - Christoph Meinel, Christian Stangier:
Modular Partitioning and Dynamic Conjunction Scheduling in Image Computation. IWLS 2002: 391-396 - Christoph Meinel, Harald Sack, Volker Schillings:
VisBDD - A Web-based Visualization Framework for OBDD Algorithms. IWLS 2002: 385-390 - Alan Mishchenko, Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177 - Alan Mishchenko, Robert K. Brayton:
Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338 - Alan Mishchenko, Marek A. Perkowski:
Logic Synthesis of Reversible Wave Cascades. IWLS 2002: 197-202 - Alan Mishchenko, Tsutomu Sasao:
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS 2002: 115-120 - Fan Mo, Robert K. Brayton:
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS 2002: 7-12 - DoRon B. Motter, Igor L. Markov:
Overcoming Resolution-Based Lower Bounds for SAT Solvers. IWLS 2002: 373-378 - Rajeev Murgai:
Net Buffering in the Presence of Multiple Timing Views. IWLS 2002: 367-372 - Leyla Nazhandali, Karem A. Sakallah:
Majority-Based Decomposition of Carry Logic in Binary Adders. IWLS 2002: 179-184 - Federico Politi:
Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD's. IWLS 2002: 221-226 - Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. IWLS 2002: 97-102 - Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain:
Improving Sequential ATPG Using SAT Methods. IWLS 2002: 79-84 - Jaijeet S. Roychowdhury:
Optical Systems 101 for EDA Practitioners. IWLS 2002: 397 - Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250 - Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384 - Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta:
Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals. IWLS 2002: 407-411 - Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis:
Comparing Transistor-Level Implementations of 4-Input Logic Functions. IWLS 2002: 361-365 - Rupesh S. Shelar, Sachin S. Sapatnekar:
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214 - Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Reversible Logic Circuit Synthesis. IWLS 2002: 125-130 - Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis. IWLS 2002: 13-20 - Hui-Yuan Song, R. Iris Bahar, Joel Grodstein:
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208 - Ankur Srivastava, Majid Sarrafzadeh:
Predictability: Definition, Analysis and Optimization. IWLS 2002: 267-272 - Cliff C. N. Sze, Ting-Chi Wang:
Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232