- Jiri Kadlec, Martin Danek:
Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC. DDECS 2006: 79-80 - Leos Kafka, Ondrej Novák:
FPGA-based Fault Simulator. DDECS 2006: 274-278 - Heikki Kariniemi, Jari Nurmi:
Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip. DDECS 2006: 186-191 - René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus:
Hardware/Software Based Hierarchical Self Test for SoCs. DDECS 2006: 159-160 - René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube:
Embedded Self Repair by Transistor and Gate Level Reconfiguration. DDECS 2006: 210-215 - Andrzej Krasniewski:
Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. DDECS 2006: 180-185 - Pavel Kubalík, Radek Dobias, Hana Kubátová:
Dependability Computation for Fault Tolerant Reconfigurable Duplex System. DDECS 2006: 100-102 - Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen:
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder. DDECS 2006: 59-64 - Harri Lampinen, Pauli Perälä, Olli Vainio:
Design of a Scalable Asynchronous Dataflow Processor. DDECS 2006: 87-88 - Régis Leveugle, V. Maingot:
On the Use of Information Redundancy When Designing Secure Chips. DDECS 2006: 141-142 - Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg:
Self-refreshing Multiple Valued Memory. DDECS 2006: 94-96 - Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg:
Multiple Valued Counter. DDECS 2006: 247-249 - Zbynek Mader, Michal Jarkovský:
SOC Diagnostic Design Using RESPIN Architecture. DDECS 2006: 241-243 - Pavol Malosek, Viera Stopjaková:
PCA Data Preprocessing for Neural Network-based Detection of Parametric Defects in Analog IC. DDECS 2006: 131-135 - Tomás Martínek, Jan Korenek, Otto Fucík, Matej Lexa:
A Flexible Technique for the Automatic Design of Approximate String Matching Architectures. DDECS 2006: 83-84 - Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak:
Can Clock Faults be Detected Through Functional Test? DDECS 2006: 168-173 - Pierre-André Mudry, Guillaume Zufferey, Gianluca Tempesti:
An Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning. DDECS 2006: 3-8 - Vladislav Nagy, Viera Stopjaková:
New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits. DDECS 2006: 236-237 - Alex Ngouanga, Gilles Sassatelli, Lionel Torres, André Borin Soares, Altamiro Amadeu Susin:
A Contextual Resources use: a Proof of Concept through the APACHES' Platform. DDECS 2006: 44-49 - Martin Novotný, Jan Schmidt:
Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve Cryptography. DDECS 2006: 145-146 - Milos Ohlídal, Josef Schwarz:
Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts. DDECS 2006: 224-225 - Ketan Paranjape:
Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience. DDECS 2006: 1 - Grzegorz Pastuszak:
Architecture Design for the Context Formatter in the H.264/AVC Encoder. DDECS 2006: 71-72 - Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina:
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS 2006: 285-289 - Aki Penttinen, Rafal P. Jastrzebski, Riku Pöllänen, Olli Pyrhönen:
Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor. DDECS 2006: 149-150 - Gergely Perlaky, Gábor Mezösi, Imre Zolomy:
Sensor Powering with Integrated MOS Compatible Solar Cell Array. DDECS 2006: 253-255 - Geguang Pu, Jifeng He, Zongyan Qiu:
An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem. DDECS 2006: 151-152 - Abid Rashid, Frank H. P. Fitzek, Ole Olsen, Morten Gade, Yannick Le Moullec:
A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication. DDECS 2006: 33-38 - Lukas Ruckay:
Recognition of DRM Signal in Frequency Domain and Hardware Demands. DDECS 2006: 73-74 - Jaume Segura:
CMOS Testing at the End of the Roadmap: Challenges and Opportunities. DDECS 2006: 2