- 2007
- Nilton B. Armstrong, Heitor S. Lopes
, Carlos Raimundo Erig Lima:
Reconfigurable Computing for Accelerating Protein Folding Simulations. ARC 2007: 314-325 - Jean-Luc Beuchat
, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto:
Multiplication over Fpm on FPGA: A Survey. ARC 2007: 214-225 - João Bispo
, Ioannis Sourdis, João M. P. Cardoso
, Stamatis Vassiliadis:
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues. ARC 2007: 179-190 - Frank Bouwens, Mladen Berekovic
, Andreas Kanstein
, Georgi Gaydadjiev
:
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. ARC 2007: 1-13 - Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton:
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. ARC 2007: 247-258 - Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo:
Image Processing Architecture for Local Features Computation. ARC 2007: 259-270 - Yazhuo Dong, Yong Dou, Jie Zhou:
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. ARC 2007: 110-121 - Yong Dou, Jinhui Xu, Guiming Wu:
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ARC 2007: 155-166 - Saar Drimer:
Authentication of FPGA Bitstreams: Why and How. ARC 2007: 73-84 - Edson Pedro Ferlin, Heitor S. Lopes
, Carlos Raimundo Erig Lima, Ederson Cichaczewski:
Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits. ARC 2007: 326-336 - Edgar Ferrer, Dorothy Bollman, Oscar Moreno:
A Fast Finite Field Multiplier. ARC 2007: 238-246 - Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis:
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. ARC 2007: 130-141 - Nicolas Hervé, Daniel Ménard, Olivier Sentieys:
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations. ARC 2007: 191-200 - Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC 2007: 343-349 - Jae Young Hur, Todor P. Stefanov
, Stephan Wong, Stamatis Vassiliadis:
Systematic Customization of On-Chip Crossbar Interconnects. ARC 2007: 61-72 - Jae Young Hur, Stephan Wong, Stamatis Vassiliadis:
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. ARC 2007: 49-60 - Ruzica Jevtic
, Carlos Carreras
, Gabriel Caffarena
:
Switching Activity Models for Power Estimation in FPGA Multipliers. ARC 2007: 201-213 - Günter Knittel:
A Compact Shader for FPGA-Based Volume Rendering Accelerators. ARC 2007: 271-282 - Yong-Min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jaehyun Park, Hanho Lee, Tae-Seon Kim
, Chong Ho Lee:
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. ARC 2007: 283-292 - Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song:
Design of a Reversible PLD Architecture. ARC 2007: 85-90 - Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho:
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. ARC 2007: 39-48 - Carlos Raimundo Erig Lima, Heitor S. Lopes
, Maiko R. Moroz, Ramon M. Menezes:
Multiple Sequence Alignment Using Reconfigurable Computing. ARC 2007: 379-384 - Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi:
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC 2007: 142-154 - Séamas McGettrick, Dermot Geraghty, Ciarán McElroy:
Searching the Web with an FPGA Based Search Engine. ARC 2007: 350-357 - Sonia Mota, Eduardo Ros, Javier Díaz, Rafael Rodríguez-Gómez, Richard R. Carrillo:
A Space Variant Mapping Architecture for Reliable Car Segmentation. ARC 2007: 337-342 - Joonseok Park, Pedro C. Diniz:
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. ARC 2007: 97-109 - Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher:
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller. ARC 2007: 373-378 - Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar Abbas Saqib, Nareli Cruz Cortés:
A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm. ARC 2007: 226-237 - Mazen A. R. Saghir, Rawan Naous:
A Configurable Multi-ported Register File Architecture for Soft Processor Cores. ARC 2007: 14-25 - Rainer Scholz:
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. ARC 2007: 122-129