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@article{DBLP:journals/tcad/Abu-IssaQ09,
author = {Abdallatif S. Abu{-}Issa and
Steven F. Quigley},
title = {Bit-Swapping {LFSR} and Scan-Chain Ordering: {A} Novel Technique for
Peak- and Average-Power Reduction in Scan-Based {BIST}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {755--759},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015736},
doi = {10.1109/TCAD.2009.2015736},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Abu-IssaQ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AcarO09,
author = {Erkan Acar and
Sule Ozev},
title = {Low-Cost Characterization and Calibration of {RF} Integrated Circuits
through {I} - {Q} Data Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {993--1005},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2020718},
doi = {10.1109/TCAD.2009.2020718},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcarO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgostaBPS09,
author = {Giovanni Agosta and
Francesco Bruschi and
Gerardo Pelosi and
Donatella Sciuto},
title = {A Transform-Parametric Approach to Boolean Matching},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {805--817},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016547},
doi = {10.1109/TCAD.2009.2016547},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgostaBPS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AhmedT09,
author = {Nisar Ahmed and
Mohammad Tehranipoor},
title = {A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering
IR-Drop Effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1573--1582},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028679},
doi = {10.1109/TCAD.2009.2028679},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AhmedT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlimondaCAPB09,
author = {Andrea Alimonda and
Salvatore Carta and
Andrea Acquaviva and
Alessandro Pisano and
Luca Benini},
title = {A Feedback-Based Approach to {DVFS} in Data-Flow Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1691--1704},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030439},
doi = {10.1109/TCAD.2009.2030439},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlimondaCAPB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlmukhaizimS09,
author = {Sobeeh Almukhaizim and
Ozgur Sinanoglu},
title = {Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During
Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {298--302},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009159},
doi = {10.1109/TCAD.2008.2009159},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AlmukhaizimS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmelifardFP09,
author = {Behnam Amelifard and
Farzan Fallah and
Massoud Pedram},
title = {Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi
Channel Lengths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {478--489},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013992},
doi = {10.1109/TCAD.2009.2013992},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AmelifardFP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmelifardP09,
author = {Behnam Amelifard and
Massoud Pedram},
title = {Optimal Design of the Power-Delivery Network for Multiple Voltage-Island
System-on-Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {888--900},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017437},
doi = {10.1109/TCAD.2009.2017437},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AmelifardP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BahukudumbiC09,
author = {Sudarshan Bahukudumbi and
Krishnendu Chakrabarty},
title = {Test-Length and {TAM} Optimization for Wafer-Level Reduced Pin-Count
Testing of Core-Based SoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {111--120},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009150},
doi = {10.1109/TCAD.2008.2009150},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BahukudumbiC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeKCCR09,
author = {Nilanjan Banerjee and
Georgios Karakonstantis and
Jung Hwan Choi and
Chaitali Chakrabarti and
Kaushik Roy},
title = {Design Methodology for Low Power and Parametric Robustness Through
Output-Quality Modulation: Application to Color-Interpolation Filtering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1127--1137},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2022197},
doi = {10.1109/TCAD.2009.2022197},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeKCCR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeSB09,
author = {Pritha Banerjee and
Susmita Sur{-}Kolay and
Arijit Bishnu},
title = {Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous
FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {651--661},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015738},
doi = {10.1109/TCAD.2009.2015738},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BangBYC09,
author = {Sung{-}Yong Bang and
Kwanhu Bang and
Sungroh Yoon and
Eui{-}Young Chung},
title = {Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1334--1347},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024706},
doi = {10.1109/TCAD.2009.2024706},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BangBYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeltrameFS09,
author = {Giovanni Beltrame and
Luca Fossati and
Donatella Sciuto},
title = {ReSP: {A} Nonintrusive Transaction-Level Reflective MPSoC Simulation
Platform for Design Space Exploration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1857--1869},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030268},
doi = {10.1109/TCAD.2009.2030268},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeltrameFS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BondD09,
author = {Bradley N. Bond and
Luca Daniel},
title = {Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear
Approximation and Projection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1467--1480},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030596},
doi = {10.1109/TCAD.2009.2030596},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BondD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrambillaGG09,
author = {Angelo Brambilla and
Giambattista Gruosso and
Giancarlo Storti Gajani},
title = {Determination of Floquet Exponents for Small-Signal Analysis of Nonlinear
Periodic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {447--451},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013285},
doi = {10.1109/TCAD.2009.2013285},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrambillaGG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BronckersSPVR09,
author = {Stephane Bronckers and
Karen Scheir and
Geert Van der Plas and
Gerd Vandersteen and
Yves Rolain},
title = {A Methodology to Predict the Impact of Substrate Noise in Analog/RF
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1613--1626},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030360},
doi = {10.1109/TCAD.2009.2030360},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BronckersSPVR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CabodiNQ09,
author = {Gianpiero Cabodi and
Sergio Nocco and
Stefano Quer},
title = {Strengthening Model Checking Techniques With Inductive Invariants},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {154--158},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009147},
doi = {10.1109/TCAD.2008.2009147},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CabodiNQ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CallegariBWA09,
author = {Nicholas Callegari and
Pouria Bastani and
Li{-}C. Wang and
Magdy S. Abadir},
title = {A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing
Mismatch},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1728--1741},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030394},
doi = {10.1109/TCAD.2009.2030394},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CallegariBWA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CarmonaCKT09,
author = {Josep Carmona and
Jordi Cortadella and
Michael Kishinevsky and
Alexander Taubin},
title = {Elastic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1437--1455},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030436},
doi = {10.1109/TCAD.2009.2030436},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CarmonaCKT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabortyB09,
author = {Rajat Subhra Chakraborty and
Swarup Bhunia},
title = {{HARPOON:} An Obfuscation-Based SoC Design Methodology for Hardware
Protection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1493--1502},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028166},
doi = {10.1109/TCAD.2009.2028166},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabortyB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangS09,
author = {Hoseok Chang and
Wonyong Sung},
title = {Access-Pattern-Aware On-Chip Memory Allocation for {SIMD} Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {158--163},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009145},
doi = {10.1109/TCAD.2008.2009145},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenC09,
author = {Jiajia Chen and
Chip{-}Hong Chang},
title = {High-Level Synthesis Algorithm for the Design of Reconfigurable Constant
Multiplier},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1844--1856},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030446},
doi = {10.1109/TCAD.2009.2030446},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCW09,
author = {Quan Chen and
Hoi Wai Choi and
Ngai Wong},
title = {Robust Simulation Methodology for Surface-Roughness Loss in Interconnect
and Package Modelings},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1654--1665},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030408},
doi = {10.1109/TCAD.2009.2030408},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenCW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCWC09,
author = {Huang{-}Yu Chen and
Szu{-}Jui Chou and
Sheng{-}Lung Wang and
Yao{-}Wen Chang},
title = {A Novel Wire-Density-Driven Full-Chip Routing System for {CMP} Variation
Control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {193--206},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009156},
doi = {10.1109/TCAD.2008.2009156},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCWC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenJ09,
author = {Duo Chen and
Dan Jiao},
title = {Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for
Electromagnetics-Based Analysis of Large-Scale Integrated Circuit
and Package Problems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1138--1149},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021010},
doi = {10.1109/TCAD.2009.2021010},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengGH09,
author = {Lerong Cheng and
Puneet Gupta and
Lei He},
title = {Efficient Additive Statistical Leakage Estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1777--1781},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030433},
doi = {10.1109/TCAD.2009.2030433},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengGH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengXH09,
author = {Lerong Cheng and
Jinjun Xiong and
Lei He},
title = {Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial
Fitting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {130--140},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009143},
doi = {10.1109/TCAD.2008.2009143},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChengXH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiouCL09,
author = {Lih{-}Yih Chiou and
Yi{-}Siou Chen and
Chih{-}Hsien Lee},
title = {System-Level Bus-Based Communication Architecture Exploration Using
a Pseudoparallel Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1213--1223},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021733},
doi = {10.1109/TCAD.2009.2021733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChiouCL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoPIDAP09,
author = {Doosan Cho and
Sudeep Pasricha and
Ilya Issenin and
Nikil D. Dutt and
Minwook Ahn and
Yunheung Paek},
title = {Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia
Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {554--567},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014002},
doi = {10.1109/TCAD.2009.2014002},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoPIDAP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoYBP09,
author = {Minsik Cho and
Kun Yuan and
Yongchan Ban and
David Z. Pan},
title = {{ELIAD:} Efficient Lithography Aware Detailed Routing Algorithm With
Compact and Macro Post-OPC Printability Prediction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1006--1016},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018876},
doi = {10.1109/TCAD.2009.2018876},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoYBP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiBR09,
author = {Jung Hwan Choi and
Nilanjan Banerjee and
Kaushik Roy},
title = {Variation-Aware Low-Power Synthesis Methodology for Fixed-Point {FIR}
Filters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {87--97},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009135},
doi = {10.1109/TCAD.2008.2009135},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiBR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiSS09,
author = {Eunjoo Choi and
Changsik Shin and
Youngsoo Shin},
title = {ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {451--456},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013283},
doi = {10.1109/TCAD.2009.2013283},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChongP09,
author = {Yee Jern Chong and
Sri Parameswaran},
title = {Custom Floating-Point Unit Generation for Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {638--650},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013999},
doi = {10.1109/TCAD.2009.2013999},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChongP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoudhuryM09,
author = {Mihir R. Choudhury and
Kartik Mohanram},
title = {Reliability Analysis of Logic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {392--405},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2012530},
doi = {10.1109/TCAD.2009.2012530},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoudhuryM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouhanBB09,
author = {Sonali Chouhan and
Ranjan Bose and
M. Balakrishnan},
title = {A Framework for Energy-Consumption-Based Design Space Exploration
for Wireless Sensor Nodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1017--1024},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018865},
doi = {10.1109/TCAD.2009.2018865},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouhanBB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuHT09,
author = {Edward T.{-}H. Chu and
Tai{-}Yi Huang and
Yu{-}Che Tsai},
title = {An Optimal Solution for the Heterogeneous Multiprocessor Single-Level
Voltage-Setup Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1705--1718},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028683},
doi = {10.1109/TCAD.2009.2028683},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuHT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChunKK09,
author = {Sunghoon Chun and
Taejin Kim and
Sungho Kang},
title = {{ATPG-XP:} Test Generation for Maximal Crosstalk-Induced Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1401--1413},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028165},
doi = {10.1109/TCAD.2009.2028165},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChunKK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CiesielskiGRGB09,
author = {Maciej J. Ciesielski and
Daniel Gomez{-}Prado and
Qian Ren and
J{\'{e}}r{\'{e}}mie Guillot and
Emmanuel Boutillon},
title = {Optimization of Data-Flow Computations Using Canonical {TED} Representation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1321--1333},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024708},
doi = {10.1109/TCAD.2009.2024708},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CiesielskiGRGB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CordoneRRSS09,
author = {Roberto Cordone and
Francesco Redaelli and
Massimo Redaelli and
Marco D. Santambrogio and
Donatella Sciuto},
title = {Partitioning and Scheduling of Task Graphs on Partially Dynamically
Reconfigurable FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {662--675},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015739},
doi = {10.1109/TCAD.2009.2015739},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CordoneRRSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CoskunRG09,
author = {Ayse Kivilcim Coskun and
Tajana Simunic Rosing and
Kenny C. Gross},
title = {Utilizing Predictors for Efficient Thermal Management in Multiprocessor
SoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1503--1516},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026357},
doi = {10.1109/TCAD.2009.2026357},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CoskunRG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CzyszKLMRT09,
author = {Dariusz Czysz and
Mark Kassab and
Xijiang Lin and
Grzegorz Mrugalski and
Janusz Rajski and
Jerzy Tyszer},
title = {Low-Power Scan Operation in Test Compression Environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1742--1755},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030445},
doi = {10.1109/TCAD.2009.2030445},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CzyszKLMRT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaiK09,
author = {Haitao Dai and
Ronald W. Knepper},
title = {Modeling and Experimental Measurement of Active Substrate-Noise Suppression
in Mixed-Signal 0.18{\(\mathrm{\mu}\)}m BiCMOS Technology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {826--836},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016545},
doi = {10.1109/TCAD.2009.2016545},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaiK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DalM09,
author = {Deniz Dal and
Nazanin Mansouri},
title = {Power Optimization With Power Islands Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1025--1037},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2020717},
doi = {10.1109/TCAD.2009.2020717},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DalM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaoudN09,
author = {Ehab Anis Daoud and
Nicola Nicolici},
title = {Real-Time Lossless Compression for Silicon Debug},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1387--1400},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023198},
doi = {10.1109/TCAD.2009.2023198},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaoudN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasSP09,
author = {Suprio Das and
Shamik Sural and
Amit Patra},
title = {Resistance Estimation for Lateral Power Arrays Through Accurate Netlist
Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {837--845},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016122},
doi = {10.1109/TCAD.2009.2016122},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasSP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DeOrioBBI09,
author = {Andrew DeOrio and
Adam Bauserman and
Valeria Bertacco and
Beth Isaksen},
title = {Inferno: Streamlining Verification With Inferred Semantics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {728--741},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013995},
doi = {10.1109/TCAD.2009.2013995},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DeOrioBBI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DhimanR09,
author = {Gaurav Dhiman and
Tajana Simunic Rosing},
title = {System-Level Power Management Using Online Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {676--689},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015740},
doi = {10.1109/TCAD.2009.2015740},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DhimanR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DongL09,
author = {Wei Dong and
Peng Li},
title = {A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following
Simulation of Driven and Autonomous Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {490--501},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014000},
doi = {10.1109/TCAD.2009.2014000},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DongL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Elfadel09,
author = {Ibrahim M. Elfadel},
title = {Convergence of Transverse Waveform Relaxation for the Electrical Analysis
of Very Wide Transmission Line Buses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1150--1161},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021729},
doi = {10.1109/TCAD.2009.2021729},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Elfadel09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EnamiNH09,
author = {Takashi Enami and
Shinyu Ninomiya and
Masanori Hashimoto},
title = {Statistical Timing Analysis Considering Spatially and Temporally Correlated
Dynamic Power Supply Noise},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {541--553},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013990},
doi = {10.1109/TCAD.2009.2013990},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/EnamiNH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ErgenSSTAAS09,
author = {Sinem Coleri Ergen and
Alberto L. Sangiovanni{-}Vincentelli and
Xuening Sun and
R. Tebano and
S. Alalusi and
G. Audisio and
Marco Sabatini},
title = {The Tire as an Intelligent Sensor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {941--955},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2022879},
doi = {10.1109/TCAD.2009.2022879},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ErgenSSTAAS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangHC09,
author = {Jia{-}Wei Fang and
Chin{-}Hsiung Hsu and
Yao{-}Wen Chang},
title = {An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {98--110},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009151},
doi = {10.1109/TCAD.2008.2009151},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FangHC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FavalliM09,
author = {Michele Favalli and
Cecilia Metra},
title = {Testing Resistive Opens and Bridging Faults Through Pulse Propagation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {915--925},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017080},
doi = {10.1109/TCAD.2009.2017080},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FavalliM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FengLZ09,
author = {Zhuo Feng and
Peng Li and
Yaping Zhan},
title = {An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order
Statistical Static Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {141--153},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2009148},
doi = {10.1109/TCAD.2009.2009148},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FengLZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FengM09,
author = {Yongfeng Feng and
H. Alan Mantooth},
title = {Algorithms for Automatic Model Topology Formulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {502--515},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013994},
doi = {10.1109/TCAD.2009.2013994},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FengM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FujiyoshiKI09,
author = {Kunihiro Fujiyoshi and
Hidenori Kawai and
Keisuke Ishihara},
title = {A Tree Based Novel Representation for 3D-Block Packing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {759--764},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015424},
doi = {10.1109/TCAD.2009.2015424},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FujiyoshiKI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GadNAZ09,
author = {Emad Gad and
Michel S. Nakhla and
Ramachandra Achar and
Yinghong Zhou},
title = {A-Stable and L-Stable High-Order Integration Methods for Solving Stiff
Differential Equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1359--1372},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024712},
doi = {10.1109/TCAD.2009.2024712},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GadNAZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GerstlauerHPSGT09,
author = {Andreas Gerstlauer and
Christian Haubelt and
Andy D. Pimentel and
Todor P. Stefanov and
Daniel D. Gajski and
J{\"{u}}rgen Teich},
title = {Electronic System-Level Synthesis Methodologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1517--1530},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026356},
doi = {10.1109/TCAD.2009.2026356},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GerstlauerHPSGT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrosseWDD09,
author = {Daniel Gro{\ss}e and
Robert Wille and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Exact Multiple-Control Toffoli Network Synthesis With {SAT} Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {703--715},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017215},
doi = {10.1109/TCAD.2009.2017215},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrosseWDD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanS09,
author = {Ki Jin Han and
Madhavan Swaminathan},
title = {Inductance and Resistance Calculations in Three-Dimensional Packaging
Using Cylindrical Conduction-Mode Basis Functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {846--859},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016642},
doi = {10.1109/TCAD.2009.2016642},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanYMNAE09,
author = {Wei Han and
Ying Yi and
Mark Muir and
Ioannis Nousias and
Tughrul Arslan and
Ahmet T. Erdogan},
title = {Multicore Architectures With Dynamically Reconfigurable Array Processors
for Wireless Broadband Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1830--1843},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2032361},
doi = {10.1109/TCAD.2009.2032361},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HanYMNAE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HarutyunyanRMS09,
author = {Davit Harutyunyan and
Joost Rommes and
E. Jan W. ter Maten and
Wil H. A. Schilders},
title = {Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1456--1466},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026359},
doi = {10.1109/TCAD.2009.2026359},
timestamp = {Tue, 08 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HarutyunyanRMS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HassanASDVY09,
author = {Zyad Hassan and
Nicholas Allec and
Li Shang and
Robert P. Dick and
V. Venkatraman and
Ronggui Yang},
title = {Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {860--873},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017428},
doi = {10.1109/TCAD.2009.2017428},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HassanASDVY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeloueAN09,
author = {Khaled R. Heloue and
Navid Azizi and
Farid N. Najm},
title = {Full-Chip Model for Leakage-Current Estimation Considering Within-Die
Correlation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {874--887},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016546},
doi = {10.1109/TCAD.2009.2016546},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeloueAN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuDTH09,
author = {Yu Hu and
Satyaki Das and
Steven Trimberger and
Lei He},
title = {Design and Synthesis of Programmable Logic Block With Mixed {LUT}
and Macrogate},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {591--595},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014001},
doi = {10.1109/TCAD.2009.2014001},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuDTH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuKH09,
author = {Shiyan Hu and
Mahesh Ketkar and
Jiang Hu},
title = {Gate Sizing for Cell-Library-Based Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {818--825},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015735},
doi = {10.1109/TCAD.2009.2015735},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuKH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangC09,
author = {Shih{-}Hsu Huang and
Chun{-}Hua Cheng},
title = {Minimum-Period Register Binding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1265--1269},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021009},
doi = {10.1109/TCAD.2009.2021009},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IngelssonAKRH09,
author = {Urban Ingelsson and
Bashir M. Al{-}Hashimi and
S. Saqib Khursheed and
Sudhakar M. Reddy and
Peter Harrod},
title = {Process Variation-Aware Test for Resistive Bridges},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1269--1274},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021728},
doi = {10.1109/TCAD.2009.2021728},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IngelssonAKRH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangG09,
author = {Zhigang Jiang and
Sandeep K. Gupta},
title = {Threshold Testing: Improving Yield for Nanoscale {VLSI}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1883--1895},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2032375},
doi = {10.1109/TCAD.2009.2032375},
timestamp = {Thu, 21 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangLJ09,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {Accurate Rank Ordering of Error Candidates for Efficient {HDL} Design
Debugging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {272--284},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009163},
doi = {10.1109/TCAD.2008.2009163},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangLJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JunYC09,
author = {Minje Jun and
Sungjoo Yoo and
Eui{-}Young Chung},
title = {Topology Synthesis of Cascaded Crossbar Switches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {926--930},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017079},
doi = {10.1109/TCAD.2009.2017079},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JunYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhursheedARH09,
author = {S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
Sudhakar M. Reddy and
Peter Harrod},
title = {Diagnosis of Multiple-Voltage Design With Bridge Defect},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {406--416},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013540},
doi = {10.1109/TCAD.2009.2013540},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KhursheedARH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimCY09,
author = {Myeongjin Kim and
Eui{-}Young Chung and
Sungroh Yoon},
title = {High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event
Evaluation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1274--1278},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2020716},
doi = {10.1109/TCAD.2009.2020716},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimCY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimOYK09,
author = {Jungsoo Kim and
Seungyong Oh and
Sungjoo Yoo and
Chong{-}Min Kyung},
title = {An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based
on Parallelism-Aware Workload and Runtime Distribution},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {568--581},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013993},
doi = {10.1109/TCAD.2009.2013993},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimOYK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KoN09,
author = {Ho Fai Ko and
Nicola Nicolici},
title = {Algorithms for State Restoration and Trace-Signal Selection for Data
Acquisition in Silicon Debug},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {285--297},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009158},
doi = {10.1109/TCAD.2008.2009158},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KoN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KrishnaswamyPMH09,
author = {Smita Krishnaswamy and
Stephen Plaza and
Igor L. Markov and
John P. Hayes},
title = {Signature-Based {SER} Analysis and Design of Logic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {74--86},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009139},
doi = {10.1109/TCAD.2008.2009139},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KrishnaswamyPMH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuoCC09,
author = {Yu{-}Min Kuo and
Yue{-}Lung Chang and
Shih{-}Chieh Chang},
title = {Efficient Boolean Characteristic Function for Timed Automatic Test
Pattern Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {417--425},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013269},
doi = {10.1109/TCAD.2009.2013269},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuoCC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuoCCM09,
author = {Yu{-}Min Kuo and
Ya{-}Ting Chang and
Shih{-}Chieh Chang and
Malgorzata Marek{-}Sadowska},
title = {Spare Cells With Constant Insertion for Engineering Change},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {456--460},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013537},
doi = {10.1109/TCAD.2009.2013537},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuoCCM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKL09,
author = {Wan Yeon Lee and
Hyogon Kim and
Heejo Lee},
title = {Maximum-Utility Scheduling of Operation Modes With Probabilistic Task
Execution Times Under Energy Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1531--1544},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026352},
doi = {10.1109/TCAD.2009.2026352},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeLC09,
author = {Wan{-}Ping Lee and
Hung{-}Yi Liu and
Yao{-}Wen Chang},
title = {Voltage-Island Partitioning and Floorplanning Under Timing Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {690--702},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013997},
doi = {10.1109/TCAD.2009.2013997},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeLC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiC09,
author = {Cheng{-}Hong Li and
Luca P. Carloni},
title = {Leveraging Local Intracore Information to Increase Global Performance
in Block-Based Design of Systems-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {165--178},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009157},
doi = {10.1109/TCAD.2008.2009157},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiKR09,
author = {Jing Li and
Kunhyuk Kang and
Kaushik Roy},
title = {Variation Estimation and Compensation Technique in Scaled {LTPS} {TFT}
Circuits for Low-Power Low-Cost Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {46--59},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009149},
doi = {10.1109/TCAD.2008.2009149},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiKR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinCL09,
author = {Mark Po{-}Hung Lin and
Yao{-}Wen Chang and
Shyh{-}Chang Lin},
title = {Analog Placement Based on Symmetry-Island Formulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {791--804},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017433},
doi = {10.1109/TCAD.2009.2017433},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LinCL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinWC09,
author = {Chen{-}Hsuan Lin and
Chun{-}Yao Wang and
Yung{-}Chih Chen},
title = {Dependent-Latch Identification in Reachable State Space},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1113--1126},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2020720},
doi = {10.1109/TCAD.2009.2020720},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinWC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuCJHZDH09,
author = {Shenghua Liu and
Guoqiang Chen and
Tom Tong Jing and
Lei He and
Tianpei Zhang and
Robi Dutta and
Xianlong Hong},
title = {Substrate Topological Routing for High-Density Packages},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {207--216},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009154},
doi = {10.1109/TCAD.2008.2009154},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuCJHZDH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuCMC09,
author = {Qiang Liu and
George A. Constantinides and
Konstantinos Masselos and
Peter Y. K. Cheung},
title = {Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted
Hardware Compilation: {A} Geometric Programming Framework},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {305--315},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013541},
doi = {10.1109/TCAD.2009.2013541},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuCMC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuS09,
author = {Qunzeng Liu and
Sachin S. Sapatnekar},
title = {A Framework for Scalable Postsilicon Statistical Delay Prediction
Under Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1201--1212},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021732},
doi = {10.1109/TCAD.2009.2021732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Macii09,
author = {Enrico Macii},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1785},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2034775},
doi = {10.1109/TCAD.2009.2034775},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Macii09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaffezzoniD09,
author = {Paolo Maffezzoni and
Dario D'Amore},
title = {Evaluating Pulling Effects in Oscillators Due to Small-Signal Injection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {22--31},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009142},
doi = {10.1109/TCAD.2008.2009142},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaffezzoniD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarculescuOPJH09,
author = {Radu Marculescu and
{\"{U}}mit Y. Ogras and
Li{-}Shiuan Peh and
Natalie D. Enright Jerger and
Yatin Vasant Hoskote},
title = {Outstanding Research Problems in NoC Design: System, Microarchitecture,
and Circuit Perspectives},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {3--21},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2010691},
doi = {10.1109/TCAD.2008.2010691},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarculescuOPJH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/McConaghyG09,
author = {Trent McConaghy and
Georges G. E. Gielen},
title = {Template-Free Symbolic Performance Modeling of Analog Circuits via
Canonical-Form Functions and Genetic Programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1162--1175},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021034},
doi = {10.1109/TCAD.2009.2021034},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/McConaghyG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/McConaghyG09a,
author = {Trent McConaghy and
Georges G. E. Gielen},
title = {Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits
via Response Surfaces and Structural Homotopy},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1627--1640},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030351},
doi = {10.1109/TCAD.2009.2030351},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/McConaghyG09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/McConaghyPSG09,
author = {Trent McConaghy and
Pieter Palmers and
Michiel Steyaert and
Georges G. E. Gielen},
title = {Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical
Building Blocks and Structural Homotopy},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1281--1294},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023195},
doi = {10.1109/TCAD.2009.2023195},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/McConaghyPSG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Meher09,
author = {Pramod Kumar Meher},
title = {Extended Sequential Logic for Synchronous Circuit Optimization and
Its Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {469--477},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014006},
doi = {10.1109/TCAD.2009.2014006},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Meher09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MehtaMTR09,
author = {Vishal J. Mehta and
Malgorzata Marek{-}Sadowska and
Kun{-}Han Tsai and
Janusz Rajski},
title = {Timing-Aware Multiple-Delay-Fault Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {245--258},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009164},
doi = {10.1109/TCAD.2008.2009164},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MehtaMTR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Micheli09,
author = {Giovanni De Micheli},
title = {An Outlook on Design Technologies for Future Integrated Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {777--790},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021008},
doi = {10.1109/TCAD.2009.2021008},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Micheli09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MogalQSB09,
author = {Hushrav Mogal and
Haifeng Qian and
Sachin S. Sapatnekar and
Kia Bazargan},
title = {Fast and Accurate Statistical Criticality Computation Under Process
Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {350--363},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013278},
doi = {10.1109/TCAD.2009.2013278},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MogalQSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MolinaRGH09,
author = {Mar{\'{\i}}a C. Molina and
Rafael Ruiz{-}Sautua and
Pedro Garcia{-}Repetto and
Rom{\'{a}}n Hermida},
title = {Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {60--73},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009140},
doi = {10.1109/TCAD.2008.2009140},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MolinaRGH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Mukhopadhyay09,
author = {S. Mukhopadhyay},
title = {A Generic Data-Driven Nonparametric Framework for Variability Analysis
of Integrated Circuits in Nanometer Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1038--1046},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017429},
doi = {10.1109/TCAD.2009.2017429},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Mukhopadhyay09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MulasAACBM09,
author = {Fabrizio Mulas and
David Atienza and
Andrea Acquaviva and
Salvatore Carta and
Luca Benini and
Giovanni De Micheli},
title = {Thermal Balancing Policy for Multiprocessor Stream Computing Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1870--1882},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2032372},
doi = {10.1109/TCAD.2009.2032372},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MulasAACBM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ObermaisserSHK09,
author = {Roman Obermaisser and
Christian El Salloum and
Bernhard Huber and
Hermann Kopetz},
title = {From a Federated to an Integrated Automotive Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {956--965},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014005},
doi = {10.1109/TCAD.2009.2014005},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ObermaisserSHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OrailogluP09,
author = {Alex Orailoglu and
Laura Pozzi},
title = {Guest Editorial Special Section on the {IEEE} Symposium on Application
Specific Processors 2008},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1786--1787},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2035481},
doi = {10.1109/TCAD.2009.2035481},
timestamp = {Mon, 15 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/OrailogluP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Ozdal09,
author = {Muhammet Mustafa Ozdal},
title = {Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {340--349},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013274},
doi = {10.1109/TCAD.2009.2013274},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Ozdal09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalW09,
author = {Muhammet Mustafa Ozdal and
Martin D. F. Wong},
title = {Archer: {A} History-Based Global Routing Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {528--540},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013991},
doi = {10.1109/TCAD.2009.2013991},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzturkKI09,
author = {Ozcan Ozturk and
Mahmut T. Kandemir and
Mary Jane Irwin},
title = {Using Data Compression for Increasing Memory System Utilization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {6},
pages = {901--914},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017430},
doi = {10.1109/TCAD.2009.2017430},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzturkKI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PalermoSZ09,
author = {Gianluca Palermo and
Cristina Silvano and
Vittorio Zaccaria},
title = {ReSPIR: {A} Response Surface-Based Pareto Iterative Refinement for
Application-Specific Design Space Exploration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1816--1829},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028681},
doi = {10.1109/TCAD.2009.2028681},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PalermoSZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkHM09,
author = {Sung{-}Boem Park and
Ted Hong and
Subhasish Mitra},
title = {Post-Silicon Bug Localization in Processors Using Instruction Footprint
Recording and Analysis {(IFRA)}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1545--1558},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030595},
doi = {10.1109/TCAD.2009.2030595},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkHM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PathakL09,
author = {Mohit Pathak and
Sung Kyu Lim},
title = {Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1373--1386},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024707},
doi = {10.1109/TCAD.2009.2024707},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PathakL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PintoCS09,
author = {Alessandro Pinto and
Luca P. Carloni and
Alberto L. Sangiovanni{-}Vincentelli},
title = {A Methodology for Constraint-Driven Synthesis of On-Chip Communications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {364--377},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013273},
doi = {10.1109/TCAD.2009.2013273},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PintoCS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional Broadside Tests Under an Expanded Definition of Functional
Operation Conditions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {121--129},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009152},
doi = {10.1109/TCAD.2008.2009152},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR09a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Double-Single Stuck-at Faults: {A} Delay Fault Model for Synchronous
Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {426--432},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013281},
doi = {10.1109/TCAD.2009.2013281},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR09b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forward-Looking Reverse Order Fault Simulation for n -Detection Test
Sets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1424--1428},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023193},
doi = {10.1109/TCAD.2009.2023193},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR09b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QinM09,
author = {Xiaoke Qin and
Prabhat Mishra},
title = {A Universal Placement Technique of Compressed Instructions for Efficient
Parallel Decompression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1224--1236},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021730},
doi = {10.1109/TCAD.2009.2021730},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QinM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaoV09,
author = {Ravishankar Rao and
Sarma B. K. Vrudhula},
title = {Fast and Accurate Prediction of the Steady-State Throughput of Multicore
Processors Under Thermal Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1559--1572},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026361},
doi = {10.1109/TCAD.2009.2026361},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaoV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RizzoliMCM09,
author = {Vittorio Rizzoli and
Franco Mastri and
Alessandra Costanzo and
Diego Masotti},
title = {Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis
of {UWB} Receivers in the Presence of Interfering Signals},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {516--527},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014004},
doi = {10.1109/TCAD.2009.2014004},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RizzoliMCM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyD09,
author = {Sourajeet Roy and
Anestis Dounavis},
title = {Closed-Form Delay and Crosstalk Models for {RLC} On-Chip Interconnects
Using a Matrix Rational Approximation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1481--1492},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026354},
doi = {10.1109/TCAD.2009.2026354},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RuggieroBBMA09,
author = {Martino Ruggiero and
Davide Bertozzi and
Luca Benini and
Michela Milano and
Alexandru Andrei},
title = {Reducing the Abstraction and Optimality Gaps in the Allocation and
Scheduling for Variable Voltage/Frequency MPSoC Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {378--391},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013536},
doi = {10.1109/TCAD.2009.2013536},
timestamp = {Wed, 24 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RuggieroBBMA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SafarpourV09,
author = {Sean Safarpour and
Andreas G. Veneris},
title = {Automated Design Debugging With Abstraction and Refinement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1597--1608},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030593},
doi = {10.1109/TCAD.2009.2030593},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SafarpourV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sangiovanni-VincentelliN09,
author = {Alberto L. Sangiovanni{-}Vincentelli and
Marco Di Natale},
title = {Challenges and Solutions in the Development of Automotive Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {937--940},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024982},
doi = {10.1109/TCAD.2009.2024982},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sangiovanni-VincentelliN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SanyalGK09,
author = {Alodeep Sanyal and
Kunal P. Ganeshpure and
Sandip Kundu},
title = {An Improved Soft-Error Rate Measurement Technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {596--600},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014003},
doi = {10.1109/TCAD.2009.2014003},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SanyalGK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SarbisheiTAF09,
author = {Omid Sarbishei and
Mahmoud Tabandeh and
Bijan Alizadeh and
Masahiro Fujita},
title = {A Formal Approach for Debugging Arithmetic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {742--754},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013998},
doi = {10.1109/TCAD.2009.2013998},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SarbisheiTAF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchlieckerRNRJE09,
author = {Simon Schliecker and
Jonas Rox and
Mircea Negrean and
Kai Richter and
Marek Jersak and
Rolf Ernst},
title = {System Level Performance Analysis for Real-Time Automotive Multicore
and Network Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {979--992},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013286},
doi = {10.1109/TCAD.2009.2013286},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchlieckerRNRJE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaS09,
author = {Dipanjan Sengupta and
Resve A. Saleh},
title = {Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip
Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {316--326},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013270},
doi = {10.1109/TCAD.2009.2013270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinPK09,
author = {Youngsoo Shin and
Seungwhun Paik and
Hyung{-}Ock Kim},
title = {Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell
Elements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {327--339},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2012532},
doi = {10.1109/TCAD.2009.2012532},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShinPK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShrivastavaIDPP09,
author = {Aviral Shrivastava and
Ilya Issenin and
Nikil D. Dutt and
Sanghyun Park and
Yunheung Paek},
title = {Compiler-in-the-Loop Design Space Exploration Framework for Energy
Reduction in Horizontally Partitioned Cache Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {461--465},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013275},
doi = {10.1109/TCAD.2009.2013275},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShrivastavaIDPP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShrivastavaKL09,
author = {Aviral Shrivastava and
Arun Kannan and
Jongeun Lee},
title = {A Software-Only Solution to Use Scratch Pads for Stack Data},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1719--1727},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030592},
doi = {10.1109/TCAD.2009.2030592},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShrivastavaKL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SingheeR09,
author = {Amith Singhee and
Rob A. Rutenbar},
title = {Statistical Blockade: Very Fast Statistical Simulation and Modeling
of Rare Circuit Events and Its Application to Memory Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1176--1189},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2020721},
doi = {10.1109/TCAD.2009.2020721},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SingheeR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinhaRVBSA09,
author = {Debjit Sinha and
Alex Rubin and
Chandu Visweswariah and
Frank Borkam and
Gregory Schaeffer and
Soroush Abbaspour},
title = {Feasible Aggressor-Set Identification Under Constraints for Maximum
Coupling Noise},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1096--1100},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018779},
doi = {10.1109/TCAD.2009.2018779},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinhaRVBSA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SovianiHE09,
author = {Cristian Soviani and
Ilija Hadzic and
Stephen A. Edwards},
title = {Synthesis and Optimization of Pipelined Packet Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {231--244},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009168},
doi = {10.1109/TCAD.2008.2009168},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SovianiHE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SpjutKKB09,
author = {Josef B. Spjut and
Andrew E. Kensler and
Daniel M. Kopta and
Erik Brunvand},
title = {TRaX: {A} Multicore Hardware Architecture for Real-Time Ray Tracing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1802--1815},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028981},
doi = {10.1109/TCAD.2009.2028981},
timestamp = {Mon, 30 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SpjutKKB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrivastavaSB09,
author = {Navin Srivastava and
Roberto Suaya and
Kaustav Banerjee},
title = {Analytical Expressions for High-Frequency {VLSI} Interconnect Impedance
Extraction in the Presence of a Multilayer Conductive Substrate},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1047--1060},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017432},
doi = {10.1109/TCAD.2009.2017432},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SrivastavaSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StevanovicM09,
author = {Ivica Stevanovic and
Colin C. McAndrew},
title = {Quadratic Backward Propagation of Variance for Nonlinear Statistical
Circuit Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1428--1432},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023194},
doi = {10.1109/TCAD.2009.2023194},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StevanovicM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StevanovicM09a,
author = {Ivica Stevanovic and
Colin C. McAndrew},
title = {Corrections to "Quadratic Backward Propagation of Variance for Nonlinear
Statistical Circuit Modeling" [Sep 09 1428-1432]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1896},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2034772},
doi = {10.1109/TCAD.2009.2034772},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StevanovicM09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StratigopoulosMB09,
author = {Haralampos{-}G. D. Stratigopoulos and
Salvador Mir and
Ahc{\`{e}}ne Bounceur},
title = {Evaluation of Analog/RF Test Measurements at the Design Stage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {582--590},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016136},
doi = {10.1109/TCAD.2009.2016136},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StratigopoulosMB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThakkerSSBRP09,
author = {Rajesh Amratlal Thakker and
Chaitanya Sathe and
Angada B. Sachid and
Maryam Shojaei Baghini and
V. Ramgopal Rao and
Mahesh B. Patil},
title = {A Novel Table-Based Approach for Design of FinFET Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1061--1070},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017431},
doi = {10.1109/TCAD.2009.2017431},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ThakkerSSBRP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TzengCH09,
author = {Chao{-}Wen Tzeng and
Han{-}Chia Cheng and
Shi{-}Yu Huang},
title = {Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {764--769},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017216},
doi = {10.1109/TCAD.2009.2017216},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TzengCH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TzengH09,
author = {Chao{-}Wen Tzeng and
Shi{-}Yu Huang},
title = {QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1756--1766},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030353},
doi = {10.1109/TCAD.2009.2030353},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TzengH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VorwerkKG09,
author = {Kristofer Vorwerk and
Andrew A. Kennings and
Jonathan W. Greene},
title = {Improving Simulated Annealing-Based {FPGA} Placement With Directed
Moves},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {179--192},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009167},
doi = {10.1109/TCAD.2008.2009167},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VorwerkKG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VytyazLHMM09,
author = {Igor Vytyaz and
David C. Lee and
Pavan Kumar Hanumolu and
Un{-}Ku Moon and
Kartikeya Mayaram},
title = {Automated Design and Optimization of Low-Noise Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {609--622},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014808},
doi = {10.1109/TCAD.2009.2014808},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VytyazLHMM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangCW09,
author = {Zhanglei Wang and
Krishnendu Chakrabarty and
Seongmoon Wang},
title = {Integrated {LFSR} Reseeding, Test-Access Optimization, and Test Scheduling
for Core-Based System-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1251--1264},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021731},
doi = {10.1109/TCAD.2009.2021731},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangCW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangDZ09,
author = {Jia Wang and
Debasish Das and
Hai Zhou},
title = {Gate Sizing by Lagrangian Relaxation Revisited},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1071--1084},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018872},
doi = {10.1109/TCAD.2009.2018872},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangDZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangFCB09,
author = {Zhanglei Wang and
Hongxia Fang and
Krishnendu Chakrabarty and
Michael Bienek},
title = {Deviation-Based {LFSR} Reseeding for Test-Data Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {259--271},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009166},
doi = {10.1109/TCAD.2008.2009166},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangFCB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangJWH09,
author = {Yifan Wang and
Stefan Joeres and
Ralf Wunderlich and
Stefan Heinen},
title = {Modeling Approaches for Functional Verification of RF-SoCs: Limits
and Future Requirements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {769--773},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2014533},
doi = {10.1109/TCAD.2009.2014533},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangJWH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLCSC09,
author = {Sying{-}Jyan Wang and
Katherine Shu{-}Min Li and
Shih{-}Cheng Chen and
Huai{-}Yan Shiu and
Yun{-}Lung Chu},
title = {Scan-Chain Partition for High Test-Data Compressibility and Low Shift
Power Under Routing Constraint},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {716--727},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2015741},
doi = {10.1109/TCAD.2009.2015741},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLCSC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangW09,
author = {Shuo Wang and
Lei Wang},
title = {Analysis of Deskew Signaling Via Adaptive Timing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {4},
pages = {601--605},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2016135},
doi = {10.1109/TCAD.2009.2016135},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangY09,
author = {Sying{-}Jyan Wang and
Tung{-}Hua Yeh},
title = {High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault
Testability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1583--1596},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026360},
doi = {10.1109/TCAD.2009.2026360},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeerasekeraPZT09,
author = {Roshan Weerasekera and
Dinesh Pamunuwa and
Li{-}Rong Zheng and
Hannu Tenhunen},
title = {Two-Dimensional and Three-Dimensional Integration of Heterogeneous
Electronic Systems Under Cost, Performance, and Technological Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1237--1250},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021734},
doi = {10.1109/TCAD.2009.2021734},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeerasekeraPZT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WilhelmGRSPF09,
author = {Reinhard Wilhelm and
Daniel Grund and
Jan Reineke and
Marc Schlickling and
Markus Pister and
Christian Ferdinand},
title = {Memory Hierarchies, Pipelines, and Buses for Future Architectures
in Time-Critical Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {966--978},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013287},
doi = {10.1109/TCAD.2009.2013287},
timestamp = {Wed, 04 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WilhelmGRSPF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuD09,
author = {Tai{-}Hsuan Wu and
Azadeh Davoodi},
title = {PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based
Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1666--1678},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2028682},
doi = {10.1109/TCAD.2009.2028682},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuHWM09,
author = {Meng{-}Fan Wu and
Jiun{-}Lang Huang and
Xiaoqing Wen and
Kohei Miyase},
title = {Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression
Environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1767--1776},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030440},
doi = {10.1109/TCAD.2009.2030440},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuHWM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuW09,
author = {Huaizhi Wu and
Martin D. F. Wong},
title = {Incremental Improvement of Voltage Assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {217--230},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009155},
doi = {10.1109/TCAD.2008.2009155},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangHXO09,
author = {Dong Xiang and
Dianwei Hu and
Qiang Xu and
Alex Orailoglu},
title = {Low-Power Scan Testing for Test Data Compression Using a Routing-Driven
Scan Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1101--1105},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018775},
doi = {10.1109/TCAD.2009.2018775},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiangHXO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieDZW09,
author = {Lin Xie and
Azadeh Davoodi and
Jun Zhang and
Tai{-}Hsuan Wu},
title = {Adjustment-Based Modeling for Timing Analysis Under Variability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1085--1095},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018874},
doi = {10.1109/TCAD.2009.2018874},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieDZW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiongZVH09,
author = {Jinjun Xiong and
Vladimir Zolotov and
Chandu Visweswariah and
Peter A. Habitz},
title = {Optimal Test Margin Computation for At-Speed Structural Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1414--1423},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024709},
doi = {10.1109/TCAD.2009.2024709},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XiongZVH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuHLPB09,
author = {Yang Xu and
Kan{-}Lin Hsiung and
Xin Li and
Lawrence T. Pileggi and
Stephen P. Boyd},
title = {Regular Analog/RF Integrated Circuits Design Using Optimization With
Recourse Including Ellipsoidal Uncertainty},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {623--637},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013996},
doi = {10.1109/TCAD.2009.2013996},
timestamp = {Tue, 12 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XuHLPB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanW09,
author = {Tan Yan and
Martin D. F. Wong},
title = {BSG-Route: {A} Length-Constrained Routing Scheme for General Planar
Topology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1679--1690},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030352},
doi = {10.1109/TCAD.2009.2030352},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YaoZ09,
author = {Haiqiong Yao and
Hao Zheng},
title = {Automated Interface Refinement for Compositional Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {433--446},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2012531},
doi = {10.1109/TCAD.2009.2012531},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YaoZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeZP09,
author = {Zuochang Ye and
Zhenhai Zhu and
Joel R. Phillips},
title = {Incremental Large-Scale Electrostatic Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1641--1653},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030267},
doi = {10.1109/TCAD.2009.2030267},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YeZP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiWSS09,
author = {Yang Yi and
R. Wenzel and
Vivek Sarin and
Weiping Shi},
title = {Inductance Extraction for Interconnects in the Presence of Nonlinear
Magnetic Materials},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {7},
pages = {1106--1110},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2018869},
doi = {10.1109/TCAD.2009.2018869},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiWSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YilmazD09,
author = {Ender Yilmaz and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Analog Layout Generator for {CMOS} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {32--45},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009137},
doi = {10.1109/TCAD.2008.2009137},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YilmazD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuhSYC09,
author = {Ping{-}Hung Yuh and
Sachin S. Sapatnekar and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1295--1306},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023196},
doi = {10.1109/TCAD.2009.2023196},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuhSYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZengL09,
author = {Zhiyu Zeng and
Peng Li},
title = {Locality-Driven Parallel Power Grid Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1190--1200},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2020719},
doi = {10.1109/TCAD.2009.2020719},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZengL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangPM09,
author = {Jie Zhang and
Nishant Patil and
Subhasish Mitra},
title = {Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant
Digital Logic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1307--1320},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023197},
doi = {10.1109/TCAD.2009.2023197},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangPM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangYHZSPZCMSIC09,
author = {Wanping Zhang and
Wenjian Yu and
Xiang Hu and
Ling Zhang and
Rui Shi and
He Peng and
Zhi Zhu and
Lew Chua{-}Eoan and
Rajeev Murgai and
Toshiyuki Shibuya and
Noriyuki Ito and
Chung{-}Kuan Cheng},
title = {Efficient Power Network Analysis Considering Multidomain Clock Gating},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1348--1358},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2024711},
doi = {10.1109/TCAD.2009.2024711},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangYHZSPZCMSIC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZuluagaT09,
author = {Marcela Zuluaga and
Nigel P. Topham},
title = {Design-Space Exploration of Resource-Sharing Solutions for Custom
Instruction Set Extensions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {12},
pages = {1788--1801},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026355},
doi = {10.1109/TCAD.2009.2026355},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZuluagaT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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