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@article{DBLP:journals/integration/AfacanLMD21,
  author       = {Engin Afacan and
                  Nuno Louren{\c{c}}o and
                  Ricardo Martins and
                  G{\"{u}}nhan D{\"{u}}ndar},
  title        = {Review: Machine learning techniques in analog/RF integrated circuit
                  design, synthesis, layout, and test},
  journal      = {Integr.},
  volume       = {77},
  pages        = {113--130},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.006},
  doi          = {10.1016/J.VLSI.2020.11.006},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/AfacanLMD21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Attarzadeh-Niaki21,
  author       = {Seyed{-}Hosein Attarzadeh{-}Niaki and
                  Ingo Sander and
                  Mohammad Ahmadi},
  title        = {An automated parallel simulation flow for cyber-physical system design},
  journal      = {Integr.},
  volume       = {77},
  pages        = {48--58},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.010},
  doi          = {10.1016/J.VLSI.2020.11.010},
  timestamp    = {Thu, 11 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Attarzadeh-Niaki21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/BanerjeeMDB21,
  author       = {Sabyasachee Banerjee and
                  Subhashis Majumder and
                  Debesh K. Das and
                  Bhargab B. Bhattacharya},
  title        = {Fast algorithms for test optimization of core based 3D SoC},
  journal      = {Integr.},
  volume       = {77},
  pages        = {70--88},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.009},
  doi          = {10.1016/J.VLSI.2020.11.009},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/BanerjeeMDB21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KatkooriIK21,
  author       = {Srinivas Katkoori and
                  Sheikh Ariful Islam and
                  Sujana Kakarla},
  title        = {Partial evaluation based triple modular redundancy for single event
                  upset mitigation},
  journal      = {Integr.},
  volume       = {77},
  pages        = {167--179},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.002},
  doi          = {10.1016/J.VLSI.2020.11.002},
  timestamp    = {Thu, 11 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KatkooriIK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KonstantinouNLD21,
  author       = {Dimitris Konstantinou and
                  Chrysostomos Nicopoulos and
                  Junghee Lee and
                  Giorgos Dimitrakopoulos},
  title        = {Multicast-enabled network-on-chip routers leveraging partitioned allocation
                  and switching},
  journal      = {Integr.},
  volume       = {77},
  pages        = {104--112},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.10.008},
  doi          = {10.1016/J.VLSI.2020.10.008},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KonstantinouNLD21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/LiPHCWCH21,
  author       = {Shuo Li and
                  Junren Pan and
                  Jin He and
                  Zhiyuan Cao and
                  Hao Wang and
                  Sheng Chang and
                  Qijun Huang},
  title        = {A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links},
  journal      = {Integr.},
  volume       = {77},
  pages        = {131--138},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.008},
  doi          = {10.1016/J.VLSI.2020.11.008},
  timestamp    = {Thu, 28 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/LiPHCWCH21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MenonKC21,
  author       = {Radhika V. Menon and
                  Shantharam Kalipatnapu and
                  Indrajit Chakrabarti},
  title        = {High speed {VLSI} architecture for improved region based active contour
                  segmentation technique},
  journal      = {Integr.},
  volume       = {77},
  pages        = {25--37},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.004},
  doi          = {10.1016/J.VLSI.2020.11.004},
  timestamp    = {Thu, 11 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MenonKC21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Moulik21,
  author       = {Sanjay Moulik},
  title        = {{RESET:} {A} real-time scheduler for energy and temperature aware
                  heterogeneous multi-core systems},
  journal      = {Integr.},
  volume       = {77},
  pages        = {59--69},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.012},
  doi          = {10.1016/J.VLSI.2020.11.012},
  timestamp    = {Thu, 11 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Moulik21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RemyaSD21,
  author       = {Jayachandran Remya and
                  P. C. Subramaniam and
                  K. J. Dhanaraj},
  title        = {A novel tunable gain {CMOS} buffer amplifier for large resistive loads},
  journal      = {Integr.},
  volume       = {77},
  pages        = {1--12},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.10.007},
  doi          = {10.1016/J.VLSI.2020.10.007},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/RemyaSD21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RoyC21,
  author       = {Subhabrata Roy and
                  Abhijit Chandra},
  title        = {A Survey of {FIR} Filter Design Techniques: Low-complexity, Narrow
                  Transition-band and Variable Bandwidth},
  journal      = {Integr.},
  volume       = {77},
  pages        = {193--204},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.12.001},
  doi          = {10.1016/J.VLSI.2020.12.001},
  timestamp    = {Thu, 11 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/RoyC21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SanatiKSM21,
  author       = {Roohollah Sanati and
                  Farzan Khatib and
                  Mohammad Javadian Sarraf and
                  Reihaneh Kardehi Moghaddam},
  title        = {Low power time-domain rail-to-rail comparator with a new delay element
                  for {ADC} applications},
  journal      = {Integr.},
  volume       = {77},
  pages        = {89--95},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.007},
  doi          = {10.1016/J.VLSI.2020.11.007},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/SanatiKSM21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SharmaBK21,
  author       = {Gaurav Sharma and
                  Lava Bhargava and
                  Vinod Kumar},
  title        = {Real-time automated register abstraction active power-aware electronic
                  system level verification framework},
  journal      = {Integr.},
  volume       = {77},
  pages        = {151--166},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.013},
  doi          = {10.1016/J.VLSI.2020.11.013},
  timestamp    = {Tue, 10 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/SharmaBK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/TorresF21,
  author       = {Jorge Alves Torres and
                  Jo{\~{a}}o Costa Freire},
  title        = {30 GHz SiGe active inductor with voltage controlled {Q}},
  journal      = {Integr.},
  volume       = {77},
  pages        = {13--24},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.003},
  doi          = {10.1016/J.VLSI.2020.11.003},
  timestamp    = {Thu, 28 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/TorresF21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/VuNN21,
  author       = {Hoang Gia Vu and
                  Takashi Nakada and
                  Yasuhiko Nakashima},
  title        = {Efficient hardware task migration for heterogeneous {FPGA} computing
                  using HDL-based checkpointing},
  journal      = {Integr.},
  volume       = {77},
  pages        = {180--192},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.011},
  doi          = {10.1016/J.VLSI.2020.11.011},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/VuNN21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/YangZMGCCY21,
  author       = {Haoyu Yang and
                  Wei Zhong and
                  Yuzhe Ma and
                  Hao Geng and
                  Ran Chen and
                  Wanli Chen and
                  Bei Yu},
  title        = {{VLSI} mask optimization: From shallow to deep learning},
  journal      = {Integr.},
  volume       = {77},
  pages        = {96--103},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.001},
  doi          = {10.1016/J.VLSI.2020.11.001},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/YangZMGCCY21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ZhangWWXZ21,
  author       = {Yuejun Zhang and
                  Jiawei Wang and
                  Pengjun Wang and
                  Xiaoyong Xue and
                  Xiaoyang Zeng},
  title        = {Orthogonal obfuscation based key management for multiple {IP} protection},
  journal      = {Integr.},
  volume       = {77},
  pages        = {139--150},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.11.005},
  doi          = {10.1016/J.VLSI.2020.11.005},
  timestamp    = {Thu, 28 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ZhangWWXZ21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ZhouCT21,
  author       = {Han Zhou and
                  Liang Chen and
                  Sheldon X.{-}D. Tan},
  title        = {Robust power grid network design considering {EM} aging effects for
                  multi-segment wires},
  journal      = {Integr.},
  volume       = {77},
  pages        = {38--47},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.vlsi.2020.10.001},
  doi          = {10.1016/J.VLSI.2020.10.001},
  timestamp    = {Wed, 28 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ZhouCT21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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