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@article{DBLP:journals/integration/BahadoriKAP16,
  author       = {Milad Bahadori and
                  Mehdi Kamal and
                  Ali Afzali{-}Kusha and
                  Massoud Pedram},
  title        = {A comparative study on performance and reliability of 32-bit binary
                  adders},
  journal      = {Integr.},
  volume       = {53},
  pages        = {54--67},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.002},
  doi          = {10.1016/J.VLSI.2015.12.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/BahadoriKAP16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/BrennaBBL16,
  author       = {Stefano Brenna and
                  Andrea Bonetti and
                  Andrea Bonfanti and
                  Andrea L. Lacaita},
  title        = {An efficient tool for the assisted design of {SAR} ADCs capacitive
                  DACs},
  journal      = {Integr.},
  volume       = {53},
  pages        = {88--99},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.005},
  doi          = {10.1016/J.VLSI.2015.12.005},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/BrennaBBL16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/HaghbayanA16,
  author       = {Mohammad Hashem Haghbayan and
                  Bijan Alizadeh},
  title        = {A dynamic specification to automatically debug and correct various
                  divider circuits},
  journal      = {Integr.},
  volume       = {53},
  pages        = {100--114},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.004},
  doi          = {10.1016/J.VLSI.2015.12.004},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/HaghbayanA16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/JiaoQK16,
  author       = {Hailong Jiao and
                  Yongmin Qiu and
                  Volkan Kursun},
  title        = {Variability-aware 7T {SRAM} circuit with low leakage high data stability
                  {SLEEP} mode},
  journal      = {Integr.},
  volume       = {53},
  pages        = {68--79},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.003},
  doi          = {10.1016/J.VLSI.2015.12.003},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/JiaoQK16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KimPKS16,
  author       = {Sangmin Kim and
                  Seungwhun Paik and
                  Seokhyeong Kang and
                  Youngsoo Shin},
  title        = {Wakeup scheduling and its buffered tree synthesis for power gating
                  circuits},
  journal      = {Integr.},
  volume       = {53},
  pages        = {157--170},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.008},
  doi          = {10.1016/J.VLSI.2015.12.008},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KimPKS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MaZLZ16,
  author       = {Ning Ma and
                  Zhuo Zou and
                  Zhonghai Lu and
                  Li{-}Rong Zheng},
  title        = {Design and implementation of multi-mode routers for large-scale inter-core
                  networks},
  journal      = {Integr.},
  volume       = {53},
  pages        = {1--13},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.10.002},
  doi          = {10.1016/J.VLSI.2015.10.002},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MaZLZ16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MahdianiSS16,
  author       = {Hoda Mahdiani and
                  Saeed Safari and
                  Mostafa E. Salehi},
  title        = {Fast and accurate FPGA-based framework for processor architecture
                  vulnerability analysis},
  journal      = {Integr.},
  volume       = {53},
  pages        = {14--26},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.11.005},
  doi          = {10.1016/J.VLSI.2015.11.005},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MahdianiSS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ParkCHS16,
  author       = {Sun{-}Mi Park and
                  Ku{-}Young Chang and
                  Dowon Hong and
                  Changho Seo},
  title        = {Explicit formulae for Mastrovito matrix and its corresponding Toeplitz
                  matrix for all irreducible pentanomials using shifted polynomial basis},
  journal      = {Integr.},
  volume       = {53},
  pages        = {27--38},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.11.004},
  doi          = {10.1016/J.VLSI.2015.11.004},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ParkCHS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SafariNK16,
  author       = {Azadeh Safari and
                  Cheeckottu Vayalil Niras and
                  Yinan Kong},
  title        = {Power-performance enhancement of two-dimensional RNS-based {DWT} image
                  processor using static voltage scaling},
  journal      = {Integr.},
  volume       = {53},
  pages        = {145--156},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.006},
  doi          = {10.1016/J.VLSI.2015.12.006},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SafariNK16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SaitS16,
  author       = {Sadiq M. Sait and
                  Umair F. Siddiqi},
  title        = {A stochastic evolution algorithm based 2D {VLSI} global router},
  journal      = {Integr.},
  volume       = {53},
  pages        = {115--125},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.007},
  doi          = {10.1016/J.VLSI.2015.12.007},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/SaitS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ShapiroAKJFF16,
  author       = {Alexander E. Shapiro and
                  Francois Atallah and
                  Kyugseok Kim and
                  Jihoon Jeong and
                  Jeff Fischer and
                  Eby G. Friedman},
  title        = {Adaptive power gating of 32-bit Kogge Stone adder},
  journal      = {Integr.},
  volume       = {53},
  pages        = {80--87},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.001},
  doi          = {10.1016/J.VLSI.2015.12.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ShapiroAKJFF16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/TsaiTHH16,
  author       = {Tsung{-}Han Tsai and
                  Pei{-}Yun Tsai and
                  Meng{-}Yuan Huang and
                  Li{-}Yang Huang},
  title        = {{WHDVI:} {A} wireless high definition video interface technique for
                  digital home},
  journal      = {Integr.},
  volume       = {53},
  pages        = {138--144},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.11.003},
  doi          = {10.1016/J.VLSI.2015.11.003},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/TsaiTHH16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/WilleSSD16,
  author       = {Robert Wille and
                  Eleonora Sch{\"{o}}nborn and
                  Mathias Soeken and
                  Rolf Drechsler},
  title        = {SyReC: {A} hardware description language for the specification and
                  synthesis of reversible circuits},
  journal      = {Integr.},
  volume       = {53},
  pages        = {39--53},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.10.001},
  doi          = {10.1016/J.VLSI.2015.10.001},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/WilleSSD16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/YangYZP16,
  author       = {Zhiming Yang and
                  Yang Yu and
                  Chengcheng Zhang and
                  Xiyuan Peng},
  title        = {NBTI-aware adaptive minimum leakage vector selection using a linear
                  programming approach},
  journal      = {Integr.},
  volume       = {53},
  pages        = {126--137},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2015.12.009},
  doi          = {10.1016/J.VLSI.2015.12.009},
  timestamp    = {Thu, 31 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/YangYZP16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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