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@article{DBLP:journals/integration/BhatiaH00,
  author       = {Dinesh Bhatia and
                  James Haralambides},
  title        = {Bounds, designs and layouts for multi-terminal {FPIC} architectures},
  journal      = {Integr.},
  volume       = {28},
  number       = {2},
  pages        = {141--156},
  year         = {2000},
  url          = {https://doi.org/10.1016/S0167-9260(99)00011-5},
  doi          = {10.1016/S0167-9260(99)00011-5},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/BhatiaH00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/DrechslerBD00,
  author       = {Rolf Drechsler and
                  Bernd Becker and
                  Nicole Drechsler},
  title        = {{OKFDD} minimization by genetic algorithms with application to circuit
                  design},
  journal      = {Integr.},
  volume       = {28},
  number       = {2},
  pages        = {121--139},
  year         = {2000},
  url          = {https://doi.org/10.1016/S0167-9260(99)00017-6},
  doi          = {10.1016/S0167-9260(99)00017-6},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/DrechslerBD00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GweeL00,
  author       = {Bah{-}Hwee Gwee and
                  Meng{-}Hiot Lim},
  title        = {A {GA} with heuristic-based decoder for {IC} floorplanning},
  journal      = {Integr.},
  volume       = {28},
  number       = {2},
  pages        = {157--172},
  year         = {2000},
  url          = {https://doi.org/10.1016/S0167-9260(99)00015-2},
  doi          = {10.1016/S0167-9260(99)00015-2},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/GweeL00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Massicotte00,
  author       = {Daniel Massicotte},
  title        = {A parallel {VLSI} architecture of Kalman-filter-based algorithms for
                  signal reconstruction},
  journal      = {Integr.},
  volume       = {28},
  number       = {2},
  pages        = {185--196},
  year         = {2000},
  url          = {https://doi.org/10.1016/S0167-9260(99)00018-8},
  doi          = {10.1016/S0167-9260(99)00018-8},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Massicotte00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Srisa-anLC00,
  author       = {Witawas Srisa{-}an and
                  Chia{-}Tien Dan Lo and
                  J. Morris Chang},
  title        = {A hardware implementation of realloc function},
  journal      = {Integr.},
  volume       = {28},
  number       = {2},
  pages        = {173--184},
  year         = {2000},
  url          = {https://doi.org/10.1016/S0167-9260(99)00016-4},
  doi          = {10.1016/S0167-9260(99)00016-4},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Srisa-anLC00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KavousianosNFG99,
  author       = {Xrysovalantis Kavousianos and
                  Dimitris Nikolos and
                  G. Foukarakis and
                  T. Gnardellis},
  title        = {New efficient totally self-checking Berger code checkers},
  journal      = {Integr.},
  volume       = {28},
  number       = {1},
  pages        = {101--118},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00013-9},
  doi          = {10.1016/S0167-9260(99)00013-9},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KavousianosNFG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MaheshwariS99,
  author       = {Naresh Maheshwari and
                  Sachin S. Sapatnekar},
  title        = {Retiming control logic},
  journal      = {Integr.},
  volume       = {28},
  number       = {1},
  pages        = {33--53},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00010-3},
  doi          = {10.1016/S0167-9260(99)00010-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MaheshwariS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/OlcozTM99,
  author       = {Katzalin Olcoz and
                  Francisco Tirado and
                  Hortensia Mecha},
  title        = {Unified data path allocation and {BIST} intrusion},
  journal      = {Integr.},
  volume       = {28},
  number       = {1},
  pages        = {55--99},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00012-7},
  doi          = {10.1016/S0167-9260(99)00012-7},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/OlcozTM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RamanathanVN99,
  author       = {S. Ramanathan and
                  V. Visvanathan and
                  S. K. Nandy},
  title        = {Synthesis of ASIPs for {DSP} algorithms},
  journal      = {Integr.},
  volume       = {28},
  number       = {1},
  pages        = {13--32},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00009-7},
  doi          = {10.1016/S0167-9260(99)00009-7},
  timestamp    = {Tue, 27 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/RamanathanVN99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Seidel99,
  author       = {Peter{-}Michael Seidel},
  title        = {High-speed redundant reciprocal approximation},
  journal      = {Integr.},
  volume       = {28},
  number       = {1},
  pages        = {1--12},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00008-5},
  doi          = {10.1016/S0167-9260(99)00008-5},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Seidel99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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