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@article{DBLP:journals/integration/DalkilicP99,
  author       = {Mehmet Emin Dalkili{\c{c}} and
                  Vijay Pitchumani},
  title        = {Multi-schedule design space exploration: an alternative synthesis
                  framework},
  journal      = {Integr.},
  volume       = {27},
  number       = {2},
  pages        = {87--112},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00007-3},
  doi          = {10.1016/S0167-9260(99)00007-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/DalkilicP99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GallantA99,
  author       = {Michael Gallant and
                  Dhamin Al{-}Khalili},
  title        = {Synthesis of low-power {CMOS} circuits using hybrid topologies},
  journal      = {Integr.},
  volume       = {27},
  number       = {2},
  pages        = {143--163},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00004-8},
  doi          = {10.1016/S0167-9260(99)00004-8},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/GallantA99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GanleyC99,
  author       = {Joseph L. Ganley and
                  James P. Cohoon},
  title        = {Provably good moat routing},
  journal      = {Integr.},
  volume       = {27},
  number       = {1},
  pages        = {47--56},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(98)00015-7},
  doi          = {10.1016/S0167-9260(98)00015-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/GanleyC99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GaoW99,
  author       = {Youxin Gao and
                  D. F. Wong},
  title        = {Shaping a {VLSI} wire to minimize Elmore delay with consideration
                  of coupling capacitance},
  journal      = {Integr.},
  volume       = {27},
  number       = {2},
  pages        = {165--178},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00005-X},
  doi          = {10.1016/S0167-9260(99)00005-X},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/GaoW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KagarisT99,
  author       = {Dimitri Kagaris and
                  Spyros Tragoudas},
  title        = {Maximum weighted independent sets on transitive graphs and applications1},
  journal      = {Integr.},
  volume       = {27},
  number       = {1},
  pages        = {77--86},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(98)00017-0},
  doi          = {10.1016/S0167-9260(98)00017-0},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KagarisT99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KimC99,
  author       = {Ytong{-}Bin Kim and
                  Tom W. Chen},
  title        = {Assessing merged DRAM/Logic technology},
  journal      = {Integr.},
  volume       = {27},
  number       = {2},
  pages        = {179--194},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00006-1},
  doi          = {10.1016/S0167-9260(99)00006-1},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KimC99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KoideW99,
  author       = {Tetsushi Koide and
                  Shin'ichi Wakabayashi},
  title        = {A timing-driven floorplanning algorithm with the Elmore delay model
                  for building block layout},
  journal      = {Integr.},
  volume       = {27},
  number       = {1},
  pages        = {57--76},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(98)00016-9},
  doi          = {10.1016/S0167-9260(98)00016-9},
  timestamp    = {Tue, 16 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/KoideW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MohnkeMM99,
  author       = {Janett Mohnke and
                  Paul Molitor and
                  Sharad Malik},
  title        = {Establishing latch correspondence for sequential circuits using distinguishing
                  signatures},
  journal      = {Integr.},
  volume       = {27},
  number       = {1},
  pages        = {33--46},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(98)00014-5},
  doi          = {10.1016/S0167-9260(98)00014-5},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/MohnkeMM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/NeumannP99,
  author       = {Ingmar Neumann and
                  Hans{-}Ulrich Post},
  title        = {Timing driven cell replication during placement for cycle time optimization},
  journal      = {Integr.},
  volume       = {27},
  number       = {2},
  pages        = {131--141},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00003-6},
  doi          = {10.1016/S0167-9260(99)00003-6},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/NeumannP99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RamanathanV99,
  author       = {S. Ramanathan and
                  V. Visvanathan},
  title        = {Low-power pipelined {LMS} adaptive filter architectures with minimal
                  adaptation delay1},
  journal      = {Integr.},
  volume       = {27},
  number       = {1},
  pages        = {1--32},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(98)00013-3},
  doi          = {10.1016/S0167-9260(98)00013-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/RamanathanV99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/StroobandtDC99,
  author       = {Dirk Stroobandt and
                  Jo Depreitere and
                  Jan Van Campenhout},
  title        = {Generating new benchmark designs using a multi-terminal net model},
  journal      = {Integr.},
  volume       = {27},
  number       = {2},
  pages        = {113--129},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-9260(99)00002-4},
  doi          = {10.1016/S0167-9260(99)00002-4},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/StroobandtDC99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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