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export results for "toc:db/conf/vlsi/vlsisoc2012s.bht:"
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@proceedings{DBLP:conf/vlsi/2012socs,
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-45073-0},
doi = {10.1007/978-3-642-45073-0},
isbn = {978-3-642-45072-3},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2012socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeanatoLMLB12a,
author = {Giulia Beanato and
Igor Loi and
Giovanni De Micheli and
Yusuf Leblebici and
Luca Benini},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Configurable Low-Latency Interconnect for Multi-core Clusters},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {107--124},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_6},
doi = {10.1007/978-3-642-45073-0\_6},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BeanatoLMLB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConstantinDAMRAB12a,
author = {Jeremy Constantin and
Ahmed Yasir Dogan and
Oskar Andersson and
Pascal Andreas Meinerzhagen and
Joachim Neves Rodrigues and
David Atienza and
Andreas Burg},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories
for Compressed Sensing},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {88--106},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_5},
doi = {10.1007/978-3-642-45073-0\_5},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ConstantinDAMRAB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GreisenSLMHGS12,
author = {Pierre Greisen and
Michael Schaffner and
Danny Luu and
Val Mikos and
Simon Heinzle and
Frank K. G{\"{u}}rkaynak and
Aljoscha Smolic},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Spatially-Varying Image Warping: Evaluations and {VLSI} Implementations},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {64--87},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_4},
doi = {10.1007/978-3-642-45073-0\_4},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GreisenSLMHGS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimG12a,
author = {Seokjoong Kim and
Matthew R. Guthaus},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array
Architecture},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {181--195},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_10},
doi = {10.1007/978-3-642-45073-0\_10},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimG12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KologeskiCKC12a,
author = {Anelise Kologeski and
Caroline Concatto and
Fernanda Lima Kastensmidt and
Luigi Carro},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Fault-Tolerant Techniques to Manage Yield and Power Constraints in
Network-on-Chip Interconnections},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {144--161},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_8},
doi = {10.1007/978-3-642-45073-0\_8},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KologeskiCKC12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MottenCP12a,
author = {Andy Motten and
Luc Claesen and
Yun Pan},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Trinocular Stereo Vision Using a Multi Level Hierarchical Classification
Structure},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {45--63},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_3},
doi = {10.1007/978-3-642-45073-0\_3},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MottenCP12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuehlberghuberKGF12,
author = {Michael Muehlberghuber and
Christoph Keller and
Frank K. G{\"{u}}rkaynak and
Norbert Felber},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {FPGA-Based High-Speed Authenticated Encryption System},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {1--20},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_1},
doi = {10.1007/978-3-642-45073-0\_1},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuehlberghuberKGF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParsanS12a,
author = {Farhad Alibeygi Parsan and
Scott C. Smith},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {{CMOS} Implementation of Threshold Gates with Hysteresis},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {196--216},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_11},
doi = {10.1007/978-3-642-45073-0\_11},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParsanS12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SabenaSR12,
author = {Davide Sabena and
Luca Sterpone and
Matteo Sonza Reorda},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {On the Automatic Generation of Software-Based Self-Test Programs for
Functional Test and Diagnosis of {VLIW} Processors},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {162--180},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_9},
doi = {10.1007/978-3-642-45073-0\_9},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SabenaSR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SpignaSJMF12a,
author = {Neil Di Spigna and
Daniel Schinke and
Srikant Jayanti and
Veena Misra and
Paul D. Franzon},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Simulation and Experimental Characterization of a Unified Memory Device
with Two Floating-Gates},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {217--233},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_12},
doi = {10.1007/978-3-642-45073-0\_12},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SpignaSJMF12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XiaoB12a,
author = {Zhibin Xiao and
Bevan M. Baas},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {A Hexagonal Processor and Interconnect Topology for Many-Core Architecture
with Dense On-Chip Networks},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {125--143},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_7},
doi = {10.1007/978-3-642-45073-0\_7},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/XiaoB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuPF12a,
author = {Qiuling Zhu and
Larry T. Pileggi and
Franz Franchetti},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {A Smart Memory Accelerated Computed Tomography Parallel Backprojection},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {21--44},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_2},
doi = {10.1007/978-3-642-45073-0\_2},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuPF12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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