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@inproceedings{DBLP:conf/iwls/AbdollahiF02,
author = {Afshin Abdollahi and
Farzan Fallah},
title = {Runtime Mechanisms for Leakage Current Reduction in {CMOS} {VLSI}
Circuits},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {419--424},
year = {2002},
timestamp = {Sun, 04 Aug 2019 18:01:44 +0200},
biburl = {https://dblp.org/rec/conf/iwls/AbdollahiF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Al-Rabadi02,
author = {Anas Al{-}Rabadi},
title = {Symmetry as a Base for a New Decomposition of Boolean Logic},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {273--278},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Al-Rabadi02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Al-RabadiC02,
author = {Anas Al{-}Rabadi and
Lee W. Casperson},
title = {Optical Realizations of Reversible Logic},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {21--26},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Al-RabadiC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/AloulMS02,
author = {Fadi A. Aloul and
Maher N. Mneimneh and
Karem A. Sakallah},
title = {ZBDD-Based Backtrack Search {SAT} Solver},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {131--136},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/AloulMS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/AloulMS02a,
author = {Fadi A. Aloul and
Igor L. Markov and
Karem A. Sakallah},
title = {Efficient Gate and Input Ordering for Circuit-to-BDD Conversion},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {137--142},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/AloulMS02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/BengtssonMD02,
author = {Tomas Bengtsson and
Andr{\'{e}}s Martinelli and
Elena Dubrova},
title = {A Fast Heuristic Algorithm for Disjunctive},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {51--56},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/BengtssonMD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/BernasconiCLP02,
author = {Anna Bernasconi and
Valentina Ciriani and
Fabrizio Luccio and
Linda Pagli},
title = {Implicit Test of Regularity for Not Completely Specified Boolean Functions},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {345--350},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/BernasconiCLP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/BystrovY02,
author = {Alexandre V. Bystrov and
Alexandre Yakovlev},
title = {Synthesis of Asynchronous Circuits with Predictable Latency},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {239--243},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/BystrovY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ChangLR02,
author = {Yen{-}Jen Chang and
Feipei Lai and
Shanq{-}Jang Ruan},
title = {An Efficient Two-Level Filter Scheme for Low Power Cache},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {61--66},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ChangLR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ChelceaN02,
author = {Tiberiu Chelcea and
Steven M. Nowick},
title = {Resynthesis and Peephole Transformations for the Optimization of Large-Scale
Asynchronous Systems},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {355--360},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ChelceaN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ChiricescuSSG02,
author = {Silviu M. S. A. Chiricescu and
Michael A. Schuette and
Herman Schmit and
Robin Glinton},
title = {Synthesis of Morphable Multipliers},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {109--113},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ChiricescuSSG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ChoC02,
author = {Geun Rae Cho and
Tom Chen},
title = {On the Impact of Fanout Optimization and Redundant Buffer Removal
for Mixed {PTL} Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {289--294},
year = {2002},
timestamp = {Mon, 02 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iwls/ChoC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/CongLL02,
author = {Jason Cong and
Joey Y. Lin and
Wangning Long},
title = {Enhanced {SPFD} Rewiring on Improving Rewiring Ability},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {91--96},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/CongLL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Cortadella02,
author = {Jordi Cortadella},
title = {Bi-Decomposition and Tree-Height Reduction for Timing Optimization},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {233--238},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Cortadella02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/DucFR02,
author = {Anh Vu Dihn Duc and
Laurent Fesquet and
Marc Renaudin},
title = {Synthesis of {QDI} Asynchronous Circuits from DTL-Style Petri-Net},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {191--196},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/DucFR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Edwards02,
author = {Stephen A. Edwards},
title = {High-Level Synthesis from the Synchronous Language Esterel},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {401--406},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Edwards02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ElgamelB02,
author = {Mohamed A. Elgamel and
Magdy A. Bayoumi},
title = {On Low Power High Level Synthesis Using Genetic Algorithms},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {37--40},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ElgamelB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Fallah02,
author = {Farzan Fallah},
title = {Binary Time Frame Expansion},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {314--319},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Fallah02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/FarmD02,
author = {Petra F{\"{a}}rm and
Elena Dubrova},
title = {Technology Mapping for Chemically Assembled Electronic Nanotechnology},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {121--124},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/FarmD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/GibbT02,
author = {S. G. Gibb and
Laurence E. Turner},
title = {The Automatic Generation of Application Specific Processors},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {161--165},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/GibbT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/HashimotoHO02,
author = {Masanori Hashimoto and
Yashiteru Hayashi and
Hidetoshi Onodera},
title = {Experimental Study on Cell-Base High-Performance Datapath Design},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {283--287},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/HashimotoHO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/JiangB02,
author = {Jie{-}Hong Roland Jiang and
Robert K. Brayton},
title = {On the Verification of Sequential Equivalence},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {307--314},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/JiangB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/JiangB02a,
author = {Yunjian Jiang and
Robert K. Brayton},
title = {Don't Care Computation in Minimizing Extended Finite State Machines
with Presburger Arithmetic},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {327--332},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/JiangB02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/JiangMB02,
author = {Jie{-}Hong Roland Jiang and
Alan Mishchenko and
Robert K. Brayton},
title = {Reducing Multi-Valued Algebraic Operations to Binary},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {339--344},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/JiangMB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KangP02,
author = {Chang Woo Kang and
Massoud Pedram},
title = {Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {295--300},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KangP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Kerntopf02,
author = {Pawel Kerntopf},
title = {An Approach to Designing Complex Reversible Logic Gates},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {31--36},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Kerntopf02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Kerntopf02a,
author = {Pawel Kerntopf},
title = {Nonlinear Sifting of Decision Diagrams},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {85--90},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Kerntopf02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KerttuLDT02,
author = {Mikael Kerttu and
Per Lindgren and
Rolf Drechsler and
Mitchell A. Thornton},
title = {Low Power Optimization Techniques for {BDD} Mapped Finite State Machines},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {143--148},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KerttuLDT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KhlopotinePK02,
author = {Andrei B. Khlopotine and
Marek A. Perkowski and
Pawel Kerntopf},
title = {Reversible Logic Synthesis by Iterative Compositions},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {261--266},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KhlopotinePK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KojimaSSKF02,
author = {Yoshihisa Kojima and
Hiroshi Saito and
Kenshu Seto and
Satoshi Komatsu and
Masahiro Fujita},
title = {Field Modifiable Architecture and its Design Methodology: System Design
Without Logic Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {103--108},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KojimaSSKF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KrenzDK02,
author = {Ren{\'{e}} Krenz and
Elena Dubrova and
Andreas Kuehlmann},
title = {Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {321--326},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KrenzDK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KudvaSD02,
author = {Prabhakar Kudva and
Andrew Sullivan and
William E. Dougherty},
title = {Metrics for Structural Logic Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {1--6},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KudvaSD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/LagadecPVFD02,
author = {Lo{\"{\i}}c Lagadec and
Bernard Pottier and
Oscar Villellas and
Erwan Fabiani and
Catherine Dezan},
title = {A {LUT} based Approach for High Level Synthesis on FPGAs},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {167--172},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/LagadecPVFD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Levitan02,
author = {Steven P. Levitan},
title = {Giga = 1/Nano: {CAD} Tools and Modeling Challenges for Giga-Scale
Mixed Technology Micro-Systems},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {399},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Levitan02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MadalinskiBY02,
author = {Agnes Madalinski and
Alexandre V. Bystrov and
Alexandre Yakovlev},
title = {Visualization of Coding Conflicts in Asynchronous Circuit Design},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {155--160},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MadalinskiBY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ManikasK02,
author = {Theodore W. Manikas and
Gerald R. Kane},
title = {Partitioning Effects on Estimated Wire Length for Mixed Macro and
Standard Cell Placement},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {27--30},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ManikasK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MeinelS02,
author = {Christoph Meinel and
Christian Stangier},
title = {Modular Partitioning and Dynamic Conjunction Scheduling in Image Computation},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {391--396},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MeinelS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MeinelSS02,
author = {Christoph Meinel and
Harald Sack and
Volker Schillings},
title = {VisBDD - {A} Web-based Visualization Framework for {OBDD} Algorithms},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {385--390},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MeinelSS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoB02,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {A Boolean Paradigm in Multi-Valued Logic Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {173--177},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoB02a,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {Simplification of Non-Deterministic Multi-Valued Networks},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {333--338},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoB02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoP02,
author = {Alan Mishchenko and
Marek A. Perkowski},
title = {Logic Synthesis of Reversible Wave Cascades},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {197--202},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoS02,
author = {Alan Mishchenko and
Tsutomu Sasao},
title = {Encoding of Boolean Functions and its Application to {LUT} Cascade
Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {115--120},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MoB02,
author = {Fan Mo and
Robert K. Brayton},
title = {Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {7--12},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MoB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MotterM02,
author = {DoRon B. Motter and
Igor L. Markov},
title = {Overcoming Resolution-Based Lower Bounds for {SAT} Solvers},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {373--378},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MotterM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Murgai02,
author = {Rajeev Murgai},
title = {Net Buffering in the Presence of Multiple Timing Views},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {367--372},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Murgai02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/NazhandaliS02,
author = {Leyla Nazhandali and
Karem A. Sakallah},
title = {Majority-Based Decomposition of Carry Logic in Binary Adders},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {179--184},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/NazhandaliS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Politi02,
author = {Federico Politi},
title = {Recognition of Transistor Level Complex Sequential and Dynamic Circuits
using State Based BDD's},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {221--226},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Politi02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/PrakashKMA02,
author = {Amit Prakash and
Ramakrishna Kotla and
Tanmoy Mandal and
Adnan Aziz},
title = {A Reconfigurable Architecture and Associated Synthesis Methodology
for High Speed Packet Classification},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {97--102},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/PrakashKMA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/PrasadHJ02,
author = {Mukul R. Prasad and
Michael S. Hsiao and
Jawahar Jain},
title = {Improving Sequential {ATPG} Using {SAT} Methods},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {79--84},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/PrasadHJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/Roychowdhury02,
author = {Jaijeet S. Roychowdhury},
title = {Optical Systems 101 for {EDA} Practitioners},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {397},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/Roychowdhury02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SaitoNFN02,
author = {Hiroshi Saito and
Hiroshi Nakamura and
Masahiro Fujita and
Takashi Nanya},
title = {Logic Optimization for Asynchronous {SI} Controllers using Transduction
Method},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {245--250},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SaitoNFN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SasaoIM02,
author = {Tsutomu Sasao and
Yukihiro Iguchi and
Munehiro Matsuura},
title = {Comparison of Decision Diagrams for Multiple-Output Logic Functions},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {379--384},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SasaoIM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SavoiuSG02,
author = {Nick Savoiu and
Sandeep K. Shukla and
Rajesh K. Gupta},
title = {Concurrency in System Level Design: Conflict Between Simulation and
Synthesis Goals},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {407--411},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SavoiuSG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SchneiderCRR02,
author = {Felipe Ribeiro Schneider and
Vin{\'{\i}}cius P. Correia and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Comparing Transistor-Level Implementations of 4-Input Logic Functions},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {361--365},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SchneiderCRR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ShelarS02,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar},
title = {Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {209--214},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ShelarS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ShendePMH02,
author = {Vivek V. Shende and
Aditya K. Prasad and
Igor L. Markov and
John P. Hayes},
title = {Reversible Logic Circuit Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {125--130},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ShendePMH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SinhaMB02,
author = {Subarnarekha Sinha and
Alan Mishchenko and
Robert K. Brayton},
title = {Topologically Constrained Logic Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {13--20},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SinhaMB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SongBG02,
author = {Hui{-}Yuan Song and
R. Iris Bahar and
Joel Grodstein},
title = {Timing Analysis for Full-Custom Circuits Using Symbolic {DC} Formulations},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {203--208},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SongBG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SrivastavaS02,
author = {Ankur Srivastava and
Majid Sarrafzadeh},
title = {Predictability: Definition, Analysis and Optimization},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {267--272},
year = {2002},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iwls/SrivastavaS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SzeW02,
author = {Cliff C. N. Sze and
Ting{-}Chi Wang},
title = {Multi-Level Circuit Clustering for Delay Minimization},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {227--232},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SzeW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/TandonP02,
author = {Amit Tandon and
Federico Politi},
title = {Model Generation and Gate Level Abstraction of Complex {CMOS} Custom
Design for Functional and {DFT} Validation},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {255--260},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/TandonP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/TangD02,
author = {Hua Tang and
Alex Doboli},
title = {Layout-Aware Synthesis Methodology for Analog Systems Based on Combined
Block Sizing, Floorplanning and Global Routing},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {41--44},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/TangD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/ThepayasuwanD02,
author = {Nattawut Thepayasuwan and
Alex Doboli},
title = {A Methodology for Core Placement and Bus Synthesis under Time, Area
and Energy Consumption Constraints},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {57--60},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/ThepayasuwanD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/TownsendTL02,
author = {Whitney J. Townsend and
Mitchell A. Thornton and
Parag K. Lala},
title = {On-line Error Detection in a Carry-free Adder},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {251--254},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/TownsendTL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/TsukisakaIN02,
author = {Masayuki Tsukisaka and
Masashi Imai and
Takashi Nanya},
title = {High Throughput Asynchronous Domino Using Dual output Buffer},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {279--282},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/TsukisakaIN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/VidalDB02,
author = {Jorgiano Vidal and
David D{\'{e}}harbe and
Dominique Borrione},
title = {Improving Static Ordering of BDDs for Reachability Analysis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {73--77},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/VidalDB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/VujkovicS02,
author = {Miodrag Vujkovic and
Carl Sechen},
title = {Optimized Power-Delay Curve Generation for Standard Cell ICs},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {413--418},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/VujkovicS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/WangSC02,
author = {Xinning Wang and
Prashant Sawkar and
Barbara A. Chappell},
title = {A Constructive Matching Algorithm for Library-Based Domino Technology
Mapping},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {215--220},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/WangSC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/YanushkevichSMD02,
author = {Svetlana N. Yanushkevich and
Vlad P. Shmerko and
V. D. Malyugin and
Piotr Dziurzanski},
title = {Linearity of World-Level Circuit Models: New Understanding},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {67--72},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/YanushkevichSMD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/YenCJ02,
author = {Chia{-}Chih Yen and
Kuang{-}Chien Chen and
Jing{-}Yang Jou},
title = {A Practical Approach to Cycle Bound Estimation for Property Checking},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {149--154},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/YenCJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/YevtushenkoVBPS02,
author = {Nina Yevtushenko and
Tiziano Villa and
Robert K. Brayton and
Alexandre Petrenko and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Equisolvability of Series vs. Controller's Topology in Synchronous
Language Equations},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {45--50},
year = {2002},
timestamp = {Tue, 15 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iwls/YevtushenkoVBPS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/YuanAAP02,
author = {Jun Yuan and
Ken Albin and
Adnan Aziz and
Carl Pixley},
title = {Simplifying Constraint Solving in Random Simulation Generation},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {185--190},
year = {2002},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iwls/YuanAAP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/YuanSHAA02,
author = {Jun Yuan and
Kurt Shultz and
John Havlicek and
Ken Albin and
Adnan Aziz},
title = {A Method for Synthesizing Boolean Constrains},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {351--353},
year = {2002},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iwls/YuanSHAA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iwls/2002,
title = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/2002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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