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@inproceedings{DBLP:conf/glvlsi/AgrawalAR96,
author = {Nidhi Agrawal and
Parul Agarwal and
C. P. Ravikumar},
title = {Efficient Delay Test Generation for Modular Circuits},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {220},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497623},
doi = {10.1109/GLSV.1996.497623},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AgrawalAR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ArunachalamAd96,
author = {Prakash Arunachalam and
Jacob A. Abraham and
Manuel A. d'Abreu},
title = {A Hierarchal Approach for Power Reduction in {VLSI} Chips},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {182},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497617},
doi = {10.1109/GLSV.1996.497617},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ArunachalamAd96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BertaccoD96,
author = {Valeria Bertacco and
Maurizio Damiani},
title = {Boolean Function Representation Using Parallel-Access Diagrams},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {112--117},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497604},
doi = {10.1109/GLSV.1996.497604},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/BertaccoD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BorahOI96,
author = {Manjit Borah and
Robert Michael Owens and
Mary Jane Irwin},
title = {Recent Developments in Performance Driven Steiner Routing: An Overview},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {137--142},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497609},
doi = {10.1109/GLSV.1996.497609},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/BorahOI96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/CarlsonCM96,
author = {Bradley S. Carlson and
C. Y. Roger Chen and
Dikran S. Meliksetian},
title = {Transistor Chaining in {CMOS} Leaf Cells of Planar Topology},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {194--199},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497619},
doi = {10.1109/GLSV.1996.497619},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/CarlsonCM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChangWP96,
author = {Yun{-}Nan Chang and
Ching{-}Yi Wang and
Keshab K. Parhi},
title = {Loop-List Scheduling for Heterogeneous Functional Units},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {2--7},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497583},
doi = {10.1109/GLSV.1996.497583},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChangWP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChantrapornchaiTS96,
author = {Chantana Chantrapornchai and
Sissades Tongsima and
Edwin Hsing{-}Mean Sha},
title = {Rapid Prototyping for Fuzzy Systems},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {234--239},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497625},
doi = {10.1109/GLSV.1996.497625},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChantrapornchaiTS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChenOT96,
author = {Guangqiu Chen and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {Timing and Power Optimization by Gate Sizing Considering False Paths},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {154},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497612},
doi = {10.1109/GLSV.1996.497612},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChenOT96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Chu96,
author = {Pong P. Chu},
title = {A Reprogrammable FPGA-Based {ATM} Traffic Generator},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {35--38},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497589},
doi = {10.1109/GLSV.1996.497589},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Chu96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Delgado-FriasNMS96,
author = {Jos{\'{e}} G. Delgado{-}Frias and
Jabulani Nyathi and
Chester L. Miller and
Douglas H. Summerville},
title = {A {VLSI} Interconnection Network Router Using a {D-CAM} with Hidden
Refresh},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {246--251},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497627},
doi = {10.1109/GLSV.1996.497627},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Delgado-FriasNMS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DesormeauxSL96,
author = {Luc Desormeaux and
Valek Szwarc and
John H. Lodge},
title = {A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {252--255},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497628},
doi = {10.1109/GLSV.1996.497628},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/DesormeauxSL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DjahanshahiAJM96,
author = {Hormoz Djahanshahi and
Majid Ahmadi and
Graham A. Jullien and
William C. Miller},
title = {Design and {VLSI} Implementation of a Unified Synapse-Neuron Architecture},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {228--233},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497624},
doi = {10.1109/GLSV.1996.497624},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DjahanshahiAJM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/EdahiroL96,
author = {Masato Edahiro and
Richard J. Lipton},
title = {Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {143--147},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497610},
doi = {10.1109/GLSV.1996.497610},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/EdahiroL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/EinspahrSA96,
author = {Kent L. Einspahr and
Sharad C. Seth and
Vishwani D. Agrawal},
title = {Improving Circuit Testability by Clock Control},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {288--293},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497635},
doi = {10.1109/GLSV.1996.497635},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/EinspahrSA96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FaragE96,
author = {Emad N. Farag and
Mohamed I. Elmasry},
title = {Low-Power Implementation of Discrete Cosine Transform},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {174--177},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497615},
doi = {10.1109/GLSV.1996.497615},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FaragE96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FerrandiFMPS96,
author = {Fabrizio Ferrandi and
Franco Fummi and
Enrico Macii and
Massimo Poncino and
Donatella Sciuto},
title = {Test Generation for Networks of Interacting FSMs Using Symbolic Techniques},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {208--213},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497621},
doi = {10.1109/GLSV.1996.497621},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FerrandiFMPS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GanleyC96,
author = {Joseph L. Ganley and
James P. Cohoon},
title = {A Provably Good Moat Routing Algorithm},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {86--85},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497599},
doi = {10.1109/GLSV.1996.497599},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GanleyC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Grewal96,
author = {Gary William Grewal},
title = {A Global Mode Instruction Minimization Technique for Embedded DSPs},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {18},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497586},
doi = {10.1109/GLSV.1996.497586},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Grewal96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Heinrich-LitanMM96,
author = {Laura Heinrich{-}Litan and
Paul Molitor and
Dirk M{\"{o}}ller},
title = {Least Upper Bounds on the Sizes of Symmetric Variable Order based
OBDDs},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {126},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497607},
doi = {10.1109/GLSV.1996.497607},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Heinrich-LitanMM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HossainTA96,
author = {Moazzem Hossain and
Bala Thumma and
Sunil Ashtaputre},
title = {A New Faster Algorithm for Iterative Placement Improvement},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497591},
doi = {10.1109/GLSV.1996.497591},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/HossainTA96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HuangCC96,
author = {Shi{-}Yu Huang and
Kwang{-}Ting Cheng and
Kuang{-}Chien Chen},
title = {On Verifying the Correctness of Retimed Circuits},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {277},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497633},
doi = {10.1109/GLSV.1996.497633},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/HuangCC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HyunY96,
author = {Jai{-}Sop Hyun and
Kwang Sub Yoon},
title = {A 3V-50MHz Analog {CMOS} Current-Mode High Frequency Filter with a
Negative Resistance Load},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {260},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497630},
doi = {10.1109/GLSV.1996.497630},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/HyunY96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Johnson96,
author = {Anthony D. Johnson},
title = {On Locally Optimal Breaking of Complex Cyclic Vertical Constraints
in {VLSI} Channel Routing},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {92--95},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497600},
doi = {10.1109/GLSV.1996.497600},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Johnson96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Kayssi96,
author = {Ayman I. Kayssi},
title = {Macromodeling {C-} and RC-loaded {CMOS} inverters for timing analysis},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {272--276},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497632},
doi = {10.1109/GLSV.1996.497632},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Kayssi96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KimS96,
author = {Seokjin Kim and
Ramalingam Sridhar},
title = {Self-Timed Mesochronous Interconnection for High-Speed {VLSI} Systems},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {122--125},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497606},
doi = {10.1109/GLSV.1996.497606},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KimS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KwiatDH96,
author = {Kevin A. Kwiat and
Warren Debany and
Salim Hariri},
title = {Software Fault Tolerance Using Dynamically Reconfigurable FPGAs},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {39},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497590},
doi = {10.1109/GLSV.1996.497590},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KwiatDH96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LillisCL96,
author = {John Lillis and
Chung{-}Kuan Cheng and
Ting{-}Ting Y. Lin},
title = {Simultaneous Routing and Buffer Insertion for High Performance Interconnect},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {148--153},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497611},
doi = {10.1109/GLSV.1996.497611},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LillisCL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LopezM96,
author = {Mario Alberto L{\'{o}}pez and
Dinesh P. Mehta},
title = {Partitioning Algorithms for Corner Stitching},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {200},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497620},
doi = {10.1109/GLSV.1996.497620},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LopezM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LoyGKM96,
author = {James Loy and
Atul Garg and
Mukkai S. Krishnamoorthy and
John F. McDonald},
title = {Chip Pad Migration is a Key Component to High Performance {MCM} Design},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {96--99},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497601},
doi = {10.1109/GLSV.1996.497601},
timestamp = {Sat, 02 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LoyGKM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MaciiP96,
author = {Enrico Macii and
Massimo Poncino},
title = {Exact Computation of the Entropy of a Logic Circuit},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {162--167},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497613},
doi = {10.1109/GLSV.1996.497613},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MaciiP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MehtaOI96,
author = {Huzefa Mehta and
Robert Michael Owens and
Mary Jane Irwin},
title = {Some Issues in Gray Code Addressing},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {178--181},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497616},
doi = {10.1109/GLSV.1996.497616},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MehtaOI96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MehtaS96,
author = {Dinesh P. Mehta and
Naveed A. Sherwani},
title = {A Minimum-Area Floorplanning Algorithm for {MBC} Designs},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {56--59},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497593},
doi = {10.1109/GLSV.1996.497593},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MehtaS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MenonJM96,
author = {Sankaran M. Menon and
Anura P. Jayasumana and
Yashwant K. Malaiya},
title = {Input Pattern Classification for Transistor Level Testing of Bridging
Faults in BiCMOS Circuits},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {214--219},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497622},
doi = {10.1109/GLSV.1996.497622},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MenonJM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NothHK96,
author = {Winfried N{\"{o}}th and
Uwe Hinsberger and
Reiner Kolla},
title = {{TROY:} {A} Tree-Based Approach to Logic Synthesis and Technology
Mapping},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {188--193},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497618},
doi = {10.1109/GLSV.1996.497618},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/NothHK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PassosS96,
author = {Nelson L. Passos and
Edwin Hsing{-}Mean Sha},
title = {A Parameterized Index-Generator for the Multi-Dimensional Interleaving
Optimization},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {66--71},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497595},
doi = {10.1109/GLSV.1996.497595},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PassosS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PetreM96,
author = {Mariana{-}Eugenia Petre and
Guido Masera},
title = {A Parametrical Architecture for Reed-Solomon Decoders},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {81},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497598},
doi = {10.1109/GLSV.1996.497598},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PetreM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzRP96,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Janak H. Patel},
title = {On Double Transition Faults as a Delay Fault Model},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {282--287},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497634},
doi = {10.1109/GLSV.1996.497634},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzRP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RathaJR96,
author = {Nalini K. Ratha and
Anil K. Jain and
Diane T. Rover},
title = {FPGA-based high performance page layout segmentation},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {29--34},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497588},
doi = {10.1109/GLSV.1996.497588},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RathaJR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RizkallaAKG96,
author = {Maher E. Rizkalla and
Richard L. Aldridge and
Nadeem A. Khan and
Harry C. Gundrum},
title = {A {CMOS} {VLSI} Implementation of an NxN Multiplexing Circuitry for
{ATM} Applications},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {256--259},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497629},
doi = {10.1109/GLSV.1996.497629},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RizkallaAKG96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RoyannezA96,
author = {Philippe Royannez and
Amara Amara},
title = {A 1.0ns 64-bits GaAs Adder using Quad tree algorithm},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {24--28},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497587},
doi = {10.1109/GLSV.1996.497587},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RoyannezA96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ShiC96,
author = {Jian{-}Feng Shi and
Liang{-}Fang Chao},
title = {Resource-Constrained Algebraic Transformation for Loop Pipelining},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {14--17},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497585},
doi = {10.1109/GLSV.1996.497585},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ShiC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ShipleySB96,
author = {Paul Shipley and
Sherif Sayed and
Magdy A. Bayoumi},
title = {A High Speed {VLSI} Architecture for Scaleable {ATM} Switches},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {72--76},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497596},
doi = {10.1109/GLSV.1996.497596},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ShipleySB96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SongCZ96,
author = {Jianjian Song and
Heng Kek Choo and
Wenjun Zhuang},
title = {A New Model for General Connectivity and its Application to Placement},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {60},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497594},
doi = {10.1109/GLSV.1996.497594},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SongCZ96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/StroobandtMC96,
author = {Dirk Stroobandt and
Herwig Van Marck and
Jan Van Campenhout},
title = {An Accurate Interconnection Length Estimation for Computer Logic},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {50--55},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497592},
doi = {10.1109/GLSV.1996.497592},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/StroobandtMC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TabriziLE96,
author = {Nozar Tabrizi and
Michael J. Liebelt and
Kamran Eshraghian},
title = {Delay Hazards in Complex Gate Based Speed Independent {VLSI} Circuits},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {266--271},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497631},
doi = {10.1109/GLSV.1996.497631},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TabriziLE96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TaharZSCL96,
author = {Sofi{\`{e}}ne Tahar and
Zijian Zhou and
Xiaoyu Song and
Eduard Cerny and
Michel Langevin},
title = {Formal Verification of an {ATM} Switch Fabric using Multiway Decision
Graphs},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {106--111},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497603},
doi = {10.1109/GLSV.1996.497603},
timestamp = {Mon, 18 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TaharZSCL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TretzZ96,
author = {Christophe Tretz and
Charles A. Zukowski},
title = {{CMOS} Transistor Sizing for Minimization of Energy-Delay Product},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {168--173},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497614},
doi = {10.1109/GLSV.1996.497614},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TretzZ96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TsaiM96,
author = {Chien{-}Chung Tsai and
Malgorzata Marek{-}Sadowska},
title = {Logic Synthesis for Testability},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {118--121},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497605},
doi = {10.1109/GLSV.1996.497605},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TsaiM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WangH96,
author = {Duen{-}Jeng Wang and
Yu Hen Hu},
title = {Synthesis of Real-Time Recursive {DSP} Algorithms Using Multiple Chips},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {8--13},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497584},
doi = {10.1109/GLSV.1996.497584},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WangH96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WangK96,
author = {Dongsheng Wang and
Ernest S. Kuh},
title = {Performance-Driven Interconnect Global Routing},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {132--136},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497608},
doi = {10.1109/GLSV.1996.497608},
timestamp = {Tue, 30 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WangK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WilbergKCRV96,
author = {J{\"{o}}rg Wilberg and
A. Kuth and
Raul Camposano and
Wolfgang Rosenstiel and
Heinrich Theodor Vierhaus},
title = {A Design Exploration Environment},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {77--80},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497597},
doi = {10.1109/GLSV.1996.497597},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WilbergKCRV96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Yan96,
author = {Jin{-}Tai Yan},
title = {An Optimal {ILP} Formulation for Minimixing the Number of Feedthrough
Cells in Standard Cell Placement},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {100},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497602},
doi = {10.1109/GLSV.1996.497602},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Yan96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YeoH96,
author = {Hangu Yeo and
Yu Hen Hu},
title = {A Modular Architecture for Real Time {HDTV} Motion Estimation with
Large Search Range},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {240},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497626},
doi = {10.1109/GLSV.1996.497626},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/YeoH96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhangM96,
author = {Zaifu Zhang and
Robert D. McLeod},
title = {An Efficient Multiple Scan Chain Testing Scheme},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {294},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497636},
doi = {10.1109/GLSV.1996.497636},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhangM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/1996,
title = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://ieeexplore.ieee.org/xpl/conhome/3536/proceeding},
isbn = {0-8186-7502-0},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/1996.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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