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@article{DBLP:journals/vlsisp/Brunvand94,
  author       = {Erik Brunvand},
  title        = {Designing self-timed systems using concurrent programs},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {47--59},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108189},
  doi          = {10.1007/BF02108189},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Brunvand94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Chu94,
  author       = {Tam{-}Anh Chu},
  title        = {Synthesis of hazard-free control circuits from asynchronous finite
                  state machines specifications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {61--84},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108190},
  doi          = {10.1007/BF02108190},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Chu94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/DeanDH94,
  author       = {Mark E. Dean and
                  David L. Dill and
                  Mark Horowitz},
  title        = {Self-timed logic using Current-Sensing Completion Detection {(CSCD)}},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {7--16},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108186},
  doi          = {10.1007/BF02108186},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/DeanDH94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/DevadasKMW94,
  author       = {Srinivas Devadas and
                  Kurt Keutzer and
                  Sharad Malik and
                  Albert R. Wang},
  title        = {Verification of asynchronous interface circuits with bounded wire
                  delays},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {161--182},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108195},
  doi          = {10.1007/BF02108195},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/DevadasKMW94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/DrerupS94,
  author       = {Ben C. Drerup and
                  Earl E. Swartzlander Jr.},
  title        = {Fast multiplier bit-product matrix reduction using bit-ordering and
                  parity generation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {249--257},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409401},
  doi          = {10.1007/BF02409401},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/DrerupS94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/FernandoE94,
  author       = {John S. Fernando and
                  Milos D. Ercegovac},
  title        = {Conventional and on-line arithmetic designs for high-speed recursive
                  digital filters},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {189--197},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409396},
  doi          = {10.1007/BF02409396},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/FernandoE94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/GopalakrishnanA94,
  author       = {Ganesh Gopalakrishnan and
                  Venkatesh Akella},
  title        = {High-level optimizations in compiling process descriptions to asynchronous
                  circuits},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {33--45},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108188},
  doi          = {10.1007/BF02108188},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/GopalakrishnanA94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/JonesS94,
  author       = {Robert F. Jones and
                  Earl E. Swartzlander Jr.},
  title        = {Parallel counter implementation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {223--232},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409399},
  doi          = {10.1007/BF02409399},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/JonesS94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KishinevskyKT94,
  author       = {Michael Kishinevsky and
                  Alex Kondratyev and
                  Alexander Taubin},
  title        = {Specification and analysis of self-timed circuits},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {117--135},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108193},
  doi          = {10.1007/BF02108193},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KishinevskyKT94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KlassFG94,
  author       = {Fabian Klass and
                  Michael J. Flynn and
                  Ad J. van de Goor},
  title        = {Fast multiplication in {VLSI} using wave pipelining techniques},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {233--248},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409400},
  doi          = {10.1007/BF02409400},
  timestamp    = {Tue, 25 May 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KlassFG94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LavagnoSS94,
  author       = {Luciano Lavagno and
                  Narendra V. Shenoy and
                  Alberto L. Sangiovanni{-}Vincentelli},
  title        = {Linear programming for hazard elimination in asynchronous circuits},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {137--160},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108194},
  doi          = {10.1007/BF02108194},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LavagnoSS94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LouieE94,
  author       = {Marianne E. Louie and
                  Milos D. Ercegovac},
  title        = {Implementing division with field programmable gate arrays},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {271--285},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409403},
  doi          = {10.1007/BF02409403},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LouieE94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MengM94,
  author       = {Teresa H. Meng and
                  Sharad Malik},
  title        = {Editorial},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {5--6},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108185},
  doi          = {10.1007/BF02108185},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MengM94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MontuschiC94,
  author       = {Paolo Montuschi and
                  Luigi Ciminiera},
  title        = {Radix-8 division with over-redundant digit set},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {259--270},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409402},
  doi          = {10.1007/BF02409402},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MontuschiC94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MoonSB94,
  author       = {Cho W. Moon and
                  Paul R. Stephan and
                  Robert K. Brayton},
  title        = {Specification, synthesis, and verification of hazard-free asynchronous
                  circuits},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {85--100},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108191},
  doi          = {10.1007/BF02108191},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MoonSB94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/OklobdzijaVS94,
  author       = {Vojin G. Oklobdzija and
                  David Villeger and
                  Thierry Soulas},
  title        = {An integrated multiplier for complex numbers},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {213--222},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409398},
  doi          = {10.1007/BF02409398},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/OklobdzijaVS94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/RaoS94,
  author       = {Poornachandra B. Rao and
                  Alexander Skavantzos},
  title        = {{ROM} based methods for computing the squaring operation in modular
                  rings},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {3},
  pages        = {199--211},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02409397},
  doi          = {10.1007/BF02409397},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/RaoS94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/VanbekbergenLGM94,
  author       = {Peter Vanbekbergen and
                  Bill Lin and
                  Gert Goossens and
                  Hugo De Man},
  title        = {A generalized state assignment theory for transformations on signal
                  transition graphs},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {101--115},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108192},
  doi          = {10.1007/BF02108192},
  timestamp    = {Mon, 01 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/VanbekbergenLGM94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Williams94,
  author       = {Ted E. Williams},
  title        = {Performance of iterative computation in self-timed rings},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {7},
  number       = {1-2},
  pages        = {17--31},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02108187},
  doi          = {10.1007/BF02108187},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Williams94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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