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@article{DBLP:journals/vlsi/AhmedSR12,
  author       = {Ashfaq Ahmed and
                  Muhammad Usman Shahid and
                  Ata ur Rehman},
  title        = {Point {DCT} {VLSI} Architecture for Emerging {HEVC} Standard},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {752024:1--752024:13},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/752024},
  doi          = {10.1155/2012/752024},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/AhmedSR12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/AssaadA12,
  author       = {Maher Assaad and
                  Mohammed H. Alser},
  title        = {Design of an All-Digital Synchronized Frequency Multiplier Based on
                  a Dual-Loop {(D/FLL)} Architecture},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {546212:1--546212:7},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/546212},
  doi          = {10.1155/2012/546212},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/AssaadA12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/AwaisC12,
  author       = {Muhammad Awais and
                  Carlo Condo},
  title        = {Flexible {LDPC} Decoder Architectures},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {730835:1--730835:16},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/730835},
  doi          = {10.1155/2012/730835},
  timestamp    = {Wed, 17 Jul 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/AwaisC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/BalasubramanianET12,
  author       = {P. Balasubramanian and
                  David A. Edwards and
                  William B. Toms},
  title        = {Redundant Logic Insertion and Latency Reduction in Self-Timed Adders},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {575389:1--575389:13},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/575389},
  doi          = {10.1155/2012/575389},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/BalasubramanianET12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/BarianiLR12,
  author       = {Massimo Bariani and
                  Paolo Lambruschini and
                  Marco Raggio},
  title        = {An Efficient Multi-Core {SIMD} Implementation for {H.264/AVC} Encoder},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {413747:1--413747:14},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/413747},
  doi          = {10.1155/2012/413747},
  timestamp    = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/BarianiLR12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/CannellaDMTS12,
  author       = {Emanuele Cannella and
                  Onur Derin and
                  Paolo Meloni and
                  Giuseppe Tuveri and
                  Todor P. Stefanov},
  title        = {Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral
                  Process Networks},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {987209:1--987209:17},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/987209},
  doi          = {10.1155/2012/987209},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/CannellaDMTS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/CorreaPDBA12,
  author       = {Guilherme Corr{\^{e}}a and
                  Daniel Palomino and
                  Cl{\'{a}}udio Machado Diniz and
                  Sergio Bampi and
                  Luciano Volcan Agostini},
  title        = {Low-Complexity Hierarchical Mode Decision Algorithms Targeting {VLSI}
                  Architecture Design for the {H.264/AVC} Video Encoder},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {748019:1--748019:20},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/748019},
  doi          = {10.1155/2012/748019},
  timestamp    = {Sat, 09 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/CorreaPDBA12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/DiamantopoulosSXS12,
  author       = {Dionysios Diamantopoulos and
                  Kostas Siozios and
                  Sotirios Xydis and
                  Dimitrios Soudris},
  title        = {A Systematic Methodology for Reliability Improvements on SoC-Based
                  Software Defined Radio Systems},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {784945:1--784945:15},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/784945},
  doi          = {10.1155/2012/784945},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/DiamantopoulosSXS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/FangLF12,
  author       = {Chia{-}Hao Fang and
                  I{-}tao Lung and
                  Chih{-}Peng Fan},
  title        = {Absolute Difference and Low-Power Bus Encoding Method for {LCD} Digital
                  Display Interfaces},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {657897:1--657897:6},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/657897},
  doi          = {10.1155/2012/657897},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/FangLF12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Gimmler-DumontKWM12,
  author       = {Christina Gimmler{-}Dumont and
                  Frank Kienle and
                  Bin Wu and
                  Guido Masera},
  title        = {A System View on Iterative {MIMO} Detection: Dynamic Sphere Detection
                  versus Fixed Effort List Detection},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {826350:1--826350:14},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/826350},
  doi          = {10.1155/2012/826350},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Gimmler-DumontKWM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/GratiKGG12,
  author       = {Khaled Grati and
                  Nadia Khouja and
                  Bertrand Le Gal and
                  Adel Ghazel},
  title        = {Power Consumption Models for Decimation {FIR} Filters in Multistandard
                  Receivers},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {870546:1--870546:15},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/870546},
  doi          = {10.1155/2012/870546},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/GratiKGG12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HuangWC12,
  author       = {Sheng{-}Chieh Huang and
                  Hui{-}Min Wang and
                  Wei{-}Yu Chen},
  title        = {A {\(\pm\)}6 ms-Accuracy, 0.68 mm\({}^{\mbox{2}}\), and 2.21 \emph{{\(\mu\)}}W
                  {QRS} Detection {ASIC}},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {809393:1--809393:13},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/809393},
  doi          = {10.1155/2012/809393},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/HuangWC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/JanJ12,
  author       = {Yahya Jan and
                  Lech J{\'{o}}zwiak},
  title        = {Communication and Memory Architecture Design of Application-Specific
                  High-End Multiprocessors},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {794753:1--794753:20},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/794753},
  doi          = {10.1155/2012/794753},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/JanJ12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/JayanthyBS12,
  author       = {S. Jayanthy and
                  M. C. Bhuvaneswari and
                  Keesarapalli Sujitha},
  title        = {Test Generation for Crosstalk-Induced Delay Faults in {VLSI} Circuits
                  Using Modified {FAN} Algorithm},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {745861:1--745861:10},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/745861},
  doi          = {10.1155/2012/745861},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/JayanthyBS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/JerbiRDA12,
  author       = {Khaled Jerbi and
                  Micka{\"{e}}l Raulet and
                  Olivier D{\'{e}}forges and
                  Mohamed Abid},
  title        = {Automatic Generation of Optimized and Synthesizable Hardware Implementation
                  from High-Level Dataflow Programs},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {298396:1--298396:14},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/298396},
  doi          = {10.1155/2012/298396},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/JerbiRDA12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/JridiAM12,
  author       = {Maher Jridi and
                  Ayman Alfalou and
                  Pramod Kumar Meher},
  title        = {Optimized Architecture Using a Novel Subexpression Elimination on
                  Loeffler Algorithm for DCT-Based Image Compression},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {209208:1--209208:12},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/209208},
  doi          = {10.1155/2012/209208},
  timestamp    = {Wed, 07 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/JridiAM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MartinaSN12,
  author       = {Maurizio Martina and
                  Muhammad Shafique and
                  Andrey Norkin},
  title        = {{VLSI} Circuits, Systems, and Architectures for Advanced Image and
                  Video Compression Standards},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {102585:1--102585:3},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/102585},
  doi          = {10.1155/2012/102585},
  timestamp    = {Tue, 29 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/MartinaSN12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MartuzaW12,
  author       = {Muhammad Martuza and
                  Khan A. Wahid},
  title        = {Low Cost Design of a Hybrid Architecture of Integer Inverse {DCT}
                  for H.264, VC-1, AVS, and {HEVC}},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {242989:1--242989:10},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/242989},
  doi          = {10.1155/2012/242989},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MartuzaW12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MaseraBKM12,
  author       = {Guido Masera and
                  Amer Baghdadi and
                  Frank Kienle and
                  Christophe Moy},
  title        = {Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {549768:1--549768:2},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/549768},
  doi          = {10.1155/2012/549768},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/MaseraBKM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MeloniPTSRL12,
  author       = {Paolo Meloni and
                  Sebastiano Pomata and
                  Giuseppe Tuveri and
                  Simone Secchi and
                  Luigi Raffo and
                  Menno Lindwer},
  title        = {Enabling Fast {ASIP} Design Space Exploration: An FPGA-Based Runtime
                  Reconfigurable Prototyper},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {580584:1--580584:16},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/580584},
  doi          = {10.1155/2012/580584},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MeloniPTSRL12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MukhopadhyayP12,
  author       = {Joyjit Mukhopadhyay and
                  Soumya Pandit},
  title        = {Modeling and Design of a Nano Scale {CMOS} Inverter for Symmetric
                  Switching Characteristics},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {505983:1--505983:13},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/505983},
  doi          = {10.1155/2012/505983},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MukhopadhyayP12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/NguyenVG12,
  author       = {Van Tam Nguyen and
                  Frederic Villain and
                  Yann Le Guillou},
  title        = {Cognitive Radio {RF:} Overview and Challenges},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {716476:1--716476:13},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/716476},
  doi          = {10.1155/2012/716476},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/NguyenVG12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Palacios-LuengasDAV12,
  author       = {Leonardo Palacios{-}Luengas and
                  Gonzalo Isaac Duchen{-}S{\'{a}}nchez and
                  Jos{\'{e}} Luis Arag{\'{o}}n{-}Vera and
                  Ruben V{\'{a}}zquez{-}Medina},
  title        = {Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {849120:1--849120:10},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/849120},
  doi          = {10.1155/2012/849120},
  timestamp    = {Mon, 29 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Palacios-LuengasDAV12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/PanXZC12,
  author       = {Min Pan and
                  Yue Xu and
                  Yanheng Zhang and
                  Chris Chu},
  title        = {FastRoute: An Efficient and High-Quality Global Router},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {608362:1--608362:18},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/608362},
  doi          = {10.1155/2012/608362},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/PanXZC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/PiscitelliP12,
  author       = {Roberta Piscitelli and
                  Andy D. Pimentel},
  title        = {A Signature-Based Power Model for MPSoC on {FPGA}},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {196984:1--196984:13},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/196984},
  doi          = {10.1155/2012/196984},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/PiscitelliP12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RakaiFBW12,
  author       = {Logan M. Rakai and
                  Amin Farshidi and
                  Laleh Behjat and
                  David T. Westwick},
  title        = {A New Length-Based Algebraic Multigrid Clustering Algorithm},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {395260:1--395260:14},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/395260},
  doi          = {10.1155/2012/395260},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RakaiFBW12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RamBP12,
  author       = {D. S. Harish Ram and
                  M. C. Bhuvaneswari and
                  Shanthi S. Prabhu},
  title        = {A Novel Framework for Applying Multiobjective {GA} and {PSO} Based
                  Approaches for Simultaneous Area, Delay, and Power Optimization in
                  High Level Synthesis of Datapaths},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {273276:1--273276:12},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/273276},
  doi          = {10.1155/2012/273276},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RamBP12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SaponaraF12,
  author       = {Sergio Saponara and
                  Luca Fanucci},
  title        = {Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip
                  Connectivity for Low-Power and Real-Time Multimedia Signal Processing},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {450302:1--450302:17},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/450302},
  doi          = {10.1155/2012/450302},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/SaponaraF12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SchlaferWWA12,
  author       = {Philipp Schl{\"{a}}fer and
                  Christian Weis and
                  Norbert Wehn and
                  Matthias Alles},
  title        = {Design Space of Flexible Multigigabit {LDPC} Decoders},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {942893:1--942893:10},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/942893},
  doi          = {10.1155/2012/942893},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/SchlaferWWA12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SinghSSS12,
  author       = {Shiwani Singh and
                  Tripti Sharma and
                  K. G. Sharma and
                  B. P. Singh},
  title        = {9T Full Adder Design in Subthreshold Region},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {248347:1--248347:5},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/248347},
  doi          = {10.1155/2012/248347},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/SinghSSS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Sundari12,
  author       = {B. Bala Tripura Sundari},
  title        = {Design Space Exploration of Deeply Nested Loop 2D Filtering and 6
                  Level {FSBM} Algorithm Mapped onto Systolic Array},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {268402:1--268402:15},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/268402},
  doi          = {10.1155/2012/268402},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Sundari12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/TtofisT12,
  author       = {Christos Ttofis and
                  Theocharis Theocharides},
  title        = {Hardware Design Considerations for Edge-Accelerated Stereo Correspondence
                  Algorithms},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {602737:1--602737:17},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/602737},
  doi          = {10.1155/2012/602737},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/TtofisT12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/WairyaNT12,
  author       = {Subodh Wairya and
                  Rajendra Kumar Nagaria and
                  Sudarshan Tiwari},
  title        = {Performance Analysis of High Speed Hybrid {CMOS} Full Adder Circuits
                  for Low Voltage {VLSI} Design},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {173079:1--173079:18},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/173079},
  doi          = {10.1155/2012/173079},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/WairyaNT12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/WaltonAGA12,
  author       = {Maxwell Walton and
                  Omar Ahmed and
                  Gary William Grewal and
                  Shawki Areibi},
  title        = {An Empirical Investigation on System and Statement Level Parallelism
                  Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {793196:1--793196:11},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/793196},
  doi          = {10.1155/2012/793196},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/WaltonAGA12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZaourarKA12,
  author       = {Lilia Zaourar and
                  Yann Kieffer and
                  Chouki Aktouf},
  title        = {A Graph-Based Approach to Optimal Scan Chain Stitching Using {RTL}
                  Design Descriptions},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {312808:1--312808:11},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/312808},
  doi          = {10.1155/2012/312808},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZaourarKA12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZhangWZZ12,
  author       = {Zhen{-}dong Zhang and
                  Bin Wu and
                  Yumei Zhou and
                  Xin Zhang},
  title        = {Low-Complexity Hardware Interleaver/Deinterleaver for {IEEE} 802.11a/g/n
                  {WLAN}},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {948957:1--948957:7},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/948957},
  doi          = {10.1155/2012/948957},
  timestamp    = {Wed, 18 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZhangWZZ12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZhaoC12,
  author       = {Xin Zhao and
                  Chris Chu},
  title        = {Line Search-Based Inverse Lithography Technique for Mask Design},
  journal      = {{VLSI} Design},
  volume       = {2012},
  pages        = {589128:1--589128:9},
  year         = {2012},
  url          = {https://doi.org/10.1155/2012/589128},
  doi          = {10.1155/2012/589128},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZhaoC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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