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@article{DBLP:journals/vlsi/0001CB95,
author = {S. Q. Zheng and
Bin Cong and
Sa{\"{\i}}d Bettayeb},
title = {Trade-Off Considerations in Designing Efficient {VLSI} Feasible Interconnection
Networks},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {365--374},
year = {1995},
url = {https://doi.org/10.1155/1995/10431},
doi = {10.1155/1995/10431},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/0001CB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/0001OB95,
author = {Sajal K. Das and
Sabine R. {\"{O}}hring and
Amit K. Banerjee},
title = {Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like
Interconnection Topology},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {335--351},
year = {1995},
url = {https://doi.org/10.1155/1995/95759},
doi = {10.1155/1995/95759},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/0001OB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AoyamaC95,
author = {Kazuhiro Aoyama and
Andrew A. Chien},
title = {The Cost of Adaptivity and Virtual Lanes in a Wormhole Router},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {315--333},
year = {1995},
url = {https://doi.org/10.1155/1995/49382},
doi = {10.1155/1995/49382},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/AoyamaC95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/DickeyK95,
author = {Susan R. Dickey and
Richard Kenner},
title = {Design of Components for a Low Cost Combining Switch},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {287--303},
year = {1995},
url = {https://doi.org/10.1155/1995/45809},
doi = {10.1155/1995/45809},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/DickeyK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/QiuA95,
author = {Ke Qiu and
Selim G. Akl},
title = {On Some Properties of the Star Graph},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {389--396},
year = {1995},
url = {https://doi.org/10.1155/1995/61390},
doi = {10.1155/1995/61390},
timestamp = {Mon, 28 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/QiuA95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/RaghunathR95,
author = {M. T. Raghunath and
Abhiram Ranade},
title = {Designing Interconnection Networks for Multi-level Packaging},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {375--388},
year = {1995},
url = {https://doi.org/10.1155/1995/57617},
doi = {10.1155/1995/57617},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/RaghunathR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SchersonC95,
author = {Isaac D. Scherson and
Chi{-}Kai Chien},
title = {Least Common Ancestor Networks},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {353--364},
year = {1995},
url = {https://doi.org/10.1155/1995/53054},
doi = {10.1155/1995/53054},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/SchersonC95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Srimani95,
author = {Pradip K. Srimani},
title = {Guest Editor's Introduction},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {i--ii},
year = {1995},
url = {https://doi.org/10.1155/1995/87424},
doi = {10.1155/1995/87424},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/Srimani95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ThompsonL95,
author = {Peter W. Thompson and
Julian D. Lewis},
title = {The {STC104} Packet Routing Chip},
journal = {{VLSI} Design},
volume = {2},
number = {4},
pages = {305--314},
year = {1995},
url = {https://doi.org/10.1155/1995/92096},
doi = {10.1155/1995/92096},
timestamp = {Thu, 31 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ThompsonL95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/00030C94,
author = {Yang Cai and
D. F. Wong and
Jason Cong},
title = {Channel Density Minimization by Pin Permutation},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {171--183},
year = {1994},
url = {https://doi.org/10.1155/1994/68279},
doi = {10.1155/1994/68279},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/00030C94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AlpertCKRS94,
author = {Charles J. Alpert and
Jason Cong and
Andrew B. Kahng and
Gabriel Robins and
Majid Sarrafzadeh},
title = {On the Minimum Density Interconnection Tree Problem},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {157--169},
year = {1994},
url = {https://doi.org/10.1155/1994/20983},
doi = {10.1155/1994/20983},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/AlpertCKRS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AshendenDM94,
author = {Peter J. Ashenden and
Henry Detmold and
Wayne S. McKeen},
title = {Execution of {VHDL} Models Using Parallel Discrete Event Simulation
Algorithms},
journal = {{VLSI} Design},
volume = {2},
number = {1},
pages = {1--16},
year = {1994},
url = {https://doi.org/10.1155/1994/86178},
doi = {10.1155/1994/86178},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/AshendenDM94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BusabaL94,
author = {Fadi Busaba and
Parag K. Lala},
title = {Techniques for Self-Checking Combinational Logic Synthesis},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {209--221},
year = {1994},
url = {https://doi.org/10.1155/1994/29238},
doi = {10.1155/1994/29238},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/BusabaL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Chen94,
author = {Chien{-}In Henry Chen},
title = {Partitioning Techniques for Built-In Self-Test Design},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {185--198},
year = {1994},
url = {https://doi.org/10.1155/1994/25656},
doi = {10.1155/1994/25656},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/Chen94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ChenT94,
author = {Cheng{-}Hsi Chen and
Ioannis G. Tollis},
title = {Area Optimization of Slicing Floorplans in Parallel},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {143--156},
year = {1994},
url = {https://doi.org/10.1155/1994/63707},
doi = {10.1155/1994/63707},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/ChenT94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/FarhatF94,
author = {Hassan Farhat and
Steven G. From},
title = {A Quadratic Programming Approach to Estimating the Testability and
Random or Deterministic Coverage of a VLSl Circuit},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {223--231},
year = {1994},
url = {https://doi.org/10.1155/1994/75615},
doi = {10.1155/1994/75615},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/FarhatF94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HudliH94,
author = {Anand V. Hudli and
Raghu V. Hudli},
title = {Temporal Logic Based Hierarchical Test Generation for Sequential {VLSI}
Circuits},
journal = {{VLSI} Design},
volume = {2},
number = {1},
pages = {69--80},
year = {1994},
url = {https://doi.org/10.1155/1994/94514},
doi = {10.1155/1994/94514},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/HudliH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HursonP94,
author = {Ali R. Hurson and
Simin H. Pakzad},
title = {Modular Scheme for Designing Special Purpose Associative Memories
and Beyond},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {267--286},
year = {1994},
url = {https://doi.org/10.1155/1994/83851},
doi = {10.1155/1994/83851},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HursonP94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Lee094,
author = {Hyung Ki Lee and
Dong S. Ha},
title = {An Efficient Automatic Test Pattern Generator for Stuck-Open Faults
in {CMOS} Combinational Circuits},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {199--207},
year = {1994},
url = {https://doi.org/10.1155/1994/71941},
doi = {10.1155/1994/71941},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/Lee094.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MahmoodHJ94,
author = {Ausif Mahmood and
Jayantha Herath and
J. Jayasumana},
title = {An Improved Data Flow Architecture for Logic Simulation Acceleration},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {259--265},
year = {1994},
url = {https://doi.org/10.1155/1994/37474},
doi = {10.1155/1994/37474},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/MahmoodHJ94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MakkiS94,
author = {Rafic Z. Makki and
Shyang{-}Tai Su},
title = {Analysis and Characterization of State Assignment Techniques for Sequential
Machines},
journal = {{VLSI} Design},
volume = {2},
number = {1},
pages = {81--88},
year = {1994},
url = {https://doi.org/10.1155/1994/51798},
doi = {10.1155/1994/51798},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/MakkiS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MaoH94,
author = {Chi{-}Yu Mao and
Yu Hen Hu},
title = {{SEGMA:} {A} Simulated Evolution Gate-Matrix Layout Algorithm},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {241--257},
year = {1994},
url = {https://doi.org/10.1155/1994/80287},
doi = {10.1155/1994/80287},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/MaoH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MuddappaMMI94,
author = {Subbu Muddappa and
Rafic Z. Makki and
Zbigniew Michalewicz and
Sridhar Isukapalli},
title = {Pioneer: {A} New Tool for Coding of Multi-Level Finite State Machines
Based on Evolution Programming},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {105--116},
year = {1994},
url = {https://doi.org/10.1155/1994/13748},
doi = {10.1155/1994/13748},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/MuddappaMMI94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ParkK94,
author = {Nohbyung Park and
Fadi J. Kurdahi},
title = {Register-Transfer Synthesis of Pipelined Data Paths},
journal = {{VLSI} Design},
volume = {2},
number = {1},
pages = {17--32},
year = {1994},
url = {https://doi.org/10.1155/1994/43564},
doi = {10.1155/1994/43564},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/ParkK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/RavikumarR94,
author = {C. P. Ravikumar and
Haroon Rasheed},
title = {{TOPS:} {A} Target-Oriented Partial Scan Design Package Based on Simulated
Annealing},
journal = {{VLSI} Design},
volume = {2},
number = {3},
pages = {233--239},
year = {1994},
url = {https://doi.org/10.1155/1994/32902},
doi = {10.1155/1994/32902},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/RavikumarR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SaabC94,
author = {Youssef Saab and
Cheng{-}Hua Chen},
title = {An Effective Solution to the Linear Placement Problem},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {117--129},
year = {1994},
url = {https://doi.org/10.1155/1994/60143},
doi = {10.1155/1994/60143},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/SaabC94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SobskiA94,
author = {Andrzej Sobski and
Alexander Albicki},
title = {High Throughput Error Control Using Parallel {CRC}},
journal = {{VLSI} Design},
volume = {2},
number = {1},
pages = {33--50},
year = {1994},
url = {https://doi.org/10.1155/1994/90841},
doi = {10.1155/1994/90841},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/SobskiA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Tragoudas94,
author = {Spyros Tragoudas},
title = {On Channel Routing Problems With Interchangeable Terminals},
journal = {{VLSI} Design},
volume = {2},
number = {1},
pages = {51--68},
year = {1994},
url = {https://doi.org/10.1155/1994/48137},
doi = {10.1155/1994/48137},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/Tragoudas94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WangCH94,
author = {Kuo{-}Hua Wang and
Cheng Chen and
Ting Ting Hwang},
title = {Technology Mapping for {FPGA} Using Generalized Functional Decomposition},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {89--103},
year = {1994},
url = {https://doi.org/10.1155/1994/56371},
doi = {10.1155/1994/56371},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/WangCH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ZhengZ94,
author = {Si{-}Qing Zheng and
Dian Zhou},
title = {Preface},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {i},
year = {1994},
url = {https://doi.org/10.1155/1994/98085},
doi = {10.1155/1994/98085},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/ZhengZ94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ZhuangLSY94,
author = {Wenjun Zhuang and
Yong Ching Lim and
Ganesh Samudra and
Neng Yan},
title = {A New Clustering Method Based on General Connectivity},
journal = {{VLSI} Design},
volume = {2},
number = {2},
pages = {131--141},
year = {1994},
url = {https://doi.org/10.1155/1994/17320},
doi = {10.1155/1994/17320},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/ZhuangLSY94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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