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@article{DBLP:journals/vlsi/AnileMR00,
author = {Angelo Marcello Anile and
Orazio Muscato and
Vittorio Romano},
title = {Moment Equations with Maximum Entropy Closure for Carrier Transport
in Semiconductor Devices: Validation in Bulk Silicon},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {335--354},
year = {2000},
url = {https://doi.org/10.1155/2000/82945},
doi = {10.1155/2000/82945},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AnileMR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BaptyNSSA00,
author = {Ted Bapty and
Sandeep Neema and
Jason Scott and
Janos Sztipanovits and
Sameh W. Asaad},
title = {Model-integrated Tools for the Design of Dynamically Reconfigurable
Systems},
journal = {{VLSI} Design},
volume = {10},
number = {3},
pages = {281--306},
year = {2000},
url = {https://doi.org/10.1155/2000/74708},
doi = {10.1155/2000/74708},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/BaptyNSSA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BattyPJS00,
author = {W. Batty and
A. J. Panks and
R. G. Johnson and
Christopher M. Snowden},
title = {Electro-thermal Modelling of Monolithic and Hybrid Microwave and Millimeter
Wave IC's},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {355--389},
year = {2000},
url = {https://doi.org/10.1155/2000/86517},
doi = {10.1155/2000/86517},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/BattyPJS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/FigueiredoGSGN00,
author = {Marco Aur{\'{e}}lio de Figueiredo and
Clay S. Gloster Jr. and
Mark A. Stephens and
Corey A. Graves and
Mouna Nakkar},
title = {Implementation of Multispectral Image Classification on a Remote Adaptive
Computer},
journal = {{VLSI} Design},
volume = {10},
number = {3},
pages = {307--319},
year = {2000},
url = {https://doi.org/10.1155/2000/31983},
doi = {10.1155/2000/31983},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/FigueiredoGSGN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Gardner00,
author = {Carl L. Gardner},
title = {Guest Editorial},
journal = {{VLSI} Design},
volume = {10},
number = {4},
year = {2000},
url = {https://doi.org/10.1155/2000/36567},
doi = {10.1155/2000/36567},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Gardner00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GardnerR00,
author = {Carl L. Gardner and
Christian A. Ringhofer},
title = {The Chapman-Enskog Expansion and the Quantum Hydrodynamic Model for
Semiconductor Devices},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {415--435},
year = {2000},
url = {https://doi.org/10.1155/2000/91289},
doi = {10.1155/2000/91289},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GardnerR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GrossVF00,
author = {Warren J. Gross and
Dragica Vasileska and
David K. Ferry},
title = {3D Simulations of Ultra-small MOSFETs with Real-space Treatment of
the Electron - Electron and Electron-ion Interactions},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {437--452},
year = {2000},
url = {https://doi.org/10.1155/2000/48474},
doi = {10.1155/2000/48474},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GrossVF00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/JeanK00,
author = {Jack Jean and
Sanjaya Kumar},
title = {Guest Editorial},
journal = {{VLSI} Design},
volume = {10},
number = {3},
year = {2000},
url = {https://doi.org/10.1155/2000/24749},
doi = {10.1155/2000/24749},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/JeanK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Jerome00,
author = {Joseph W. Jerome},
title = {Analytical and Computational Advances for Hydrodynamic Models of Classical
and Quantum Charge Transport},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {453--466},
year = {2000},
url = {https://doi.org/10.1155/2000/94851},
doi = {10.1155/2000/94851},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Jerome00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LuoMA00,
author = {Zhen Luo and
Margaret Martonosi and
Pranav Ashar},
title = {An Edge-endpoint-based Configurable Hardware Architecture for {VLSI}
Layout Design Rule Checking},
journal = {{VLSI} Design},
volume = {10},
number = {3},
pages = {249--263},
year = {2000},
url = {https://doi.org/10.1155/2000/71046},
doi = {10.1155/2000/71046},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LuoMA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ReggianiVCRB00,
author = {Susanna Reggiani and
Marina Valdinoci and
Luigi Colalongo and
Massimo Rudan and
Giorgio Baccarani},
title = {An Analytical, Temperature-dependent Model for Majority- and Minority-carrier
Mobility in Silicon Devices},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {467--483},
year = {2000},
url = {https://doi.org/10.1155/2000/52147},
doi = {10.1155/2000/52147},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ReggianiVCRB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SchottCPCCCFHTV00,
author = {Brian Schott and
Stephen P. Crago and
Robert Parker and
Chen H. Chen and
Lauretta C. Carter and
Joseph Czarnaski and
Matthew French and
Ivan Hom and
Tam Tho and
Terri Valenti},
title = {Reconfigurable Architectures for System Level Applications of Adaptive
Computing},
journal = {{VLSI} Design},
volume = {10},
number = {3},
pages = {265--279},
year = {2000},
url = {https://doi.org/10.1155/2000/28323},
doi = {10.1155/2000/28323},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/SchottCPCCCFHTV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WuW00,
author = {Chi{-}Feng Wu and
Cheng{-}Wen Wu},
title = {Testing and Diagnosing Dynamic Reconfigurable {FPGA}},
journal = {{VLSI} Design},
volume = {10},
number = {3},
pages = {321--333},
year = {2000},
url = {https://doi.org/10.1155/2000/79281},
doi = {10.1155/2000/79281},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WuW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/X00,
title = {Advanced Numerical Methods and Software Approaches for Semiconductor
Device Simulation},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {391--414},
year = {2000},
url = {https://doi.org/10.1155/2000/43903},
doi = {10.1155/2000/43903},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/X00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/X00a,
author = {Donald J. Rose and
Hai Shao and
Craig S. Henriquez},
title = {Discretization of Anisotropic Convection-diffusion Equations, Convective
M-matrices and their Iterative Solution},
journal = {{VLSI} Design},
volume = {10},
number = {4},
pages = {485--529},
year = {2000},
url = {https://doi.org/10.1155/2000/98424},
doi = {10.1155/2000/98424},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/X00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AlpertCCHKMM99,
author = {Charles J. Alpert and
Andrew E. Caldwell and
Tony F. Chan and
Dennis J.{-}H. Huang and
Andrew B. Kahng and
Igor L. Markov and
M. S. Moroz},
title = {Analytical Engines are Unnecessary in Top-down Partitioning-based
Placement},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {99--116},
year = {1999},
url = {https://doi.org/10.1155/1999/93607},
doi = {10.1155/1999/93607},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AlpertCCHKMM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AshendenW99,
author = {Peter J. Ashenden and
Philip A. Wilsey},
title = {Principles for Language Extensions to {VHDL} to Support High-Level
Modeling},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {217--235},
year = {1999},
url = {https://doi.org/10.1155/1999/20186},
doi = {10.1155/1999/20186},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AshendenW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ChengS99,
author = {Edward Y. C. Cheng and
Sartaj Sahni},
title = {A Fast Algorithm for Performance-Driven Module Implementation Selection},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {237--247},
year = {1999},
url = {https://doi.org/10.1155/1999/67373},
doi = {10.1155/1999/67373},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ChengS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Cho99,
author = {Jun{-}Dong Cho},
title = {Preface},
journal = {{VLSI} Design},
volume = {10},
number = {1},
year = {1999},
url = {https://doi.org/10.1155/1999/35313},
doi = {10.1155/1999/35313},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Cho99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Chrzanowska-Jeske99,
author = {Malgorzata Chrzanowska{-}Jeske and
Yang Xu and
Marek A. Perkowski},
title = {Logic Synthesis for a Regular Layout},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {35--55},
year = {1999},
url = {https://doi.org/10.1155/1999/85272},
doi = {10.1155/1999/85272},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Chrzanowska-Jeske99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/John99,
author = {Lizy Kurian John},
title = {Memory Chips with Adjustable Configurations},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {203--215},
year = {1999},
url = {https://doi.org/10.1155/1999/62801},
doi = {10.1155/1999/62801},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/John99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/KahngMS99,
author = {Andrew B. Kahng and
Sudhakar Muddu and
Egino Sarto},
title = {Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron
ICs},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {21--34},
year = {1999},
url = {https://doi.org/10.1155/1999/38974},
doi = {10.1155/1999/38974},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/KahngMS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/KimS99,
author = {Wonjong Kim and
Hyunchul Shin},
title = {Hierarchy Restructuring for Hierarchical {LVS} Comparison},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {117--125},
year = {1999},
url = {https://doi.org/10.1155/1999/50892},
doi = {10.1155/1999/50892},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/KimS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MasselosMSG99,
author = {Kostas Masselos and
Panagiotis Merakos and
Thanos Stouraitis and
Constantinos E. Goutis},
title = {Computation Reordering: {A} Novel Transformation for Low Power {DSP}
Synthesis},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {177--202},
year = {1999},
url = {https://doi.org/10.1155/1999/16415},
doi = {10.1155/1999/16415},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/MasselosMSG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/NamCW99,
author = {S.{-}H. Nam and
J. D. Cho and
D. Wagner},
title = {Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout
Design},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {87--97},
year = {1999},
url = {https://doi.org/10.1155/1999/47230},
doi = {10.1155/1999/47230},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/NamCW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Stroele99,
author = {Albrecht P. Stroele},
title = {Signature Analysis for Test Responses of Sequential Circuits},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {127--141},
year = {1999},
url = {https://doi.org/10.1155/1999/97179},
doi = {10.1155/1999/97179},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Stroele99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/StroobandtC99,
author = {Dirk Stroobandt and
Jan Van Campenhout},
title = {Accurate Interconnection Length Estimations for Predictions Early
in the Design Cycle},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {1--20},
year = {1999},
url = {https://doi.org/10.1155/1999/81698},
doi = {10.1155/1999/81698},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/StroobandtC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WangBS99,
author = {Maogang Wang and
Prithviraj Banerjee and
Majid Sarrafzadeh},
title = {Placement with Incomplete Data},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {57--70},
year = {1999},
url = {https://doi.org/10.1155/1999/42648},
doi = {10.1155/1999/42648},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WangBS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WuT99,
author = {Wen{-}Jer Wu and
Chuan Yi Tang},
title = {Automatic Test Timing Assignment for RAMs Using Linear Programming},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {143--153},
year = {1999},
url = {https://doi.org/10.1155/1999/54564},
doi = {10.1155/1999/54564},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WuT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/XuGC99,
author = {Jin Xu and
Pei{-}Ning Guo and
Chung{-}Kuan Cheng},
title = {Empirical Study of Block Placement by Cluster Refinement},
journal = {{VLSI} Design},
volume = {10},
number = {1},
pages = {71--86},
year = {1999},
url = {https://doi.org/10.1155/1999/89835},
doi = {10.1155/1999/89835},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/XuGC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Yan99,
author = {Jin{-}Tai Yan},
title = {Routability Crossing Distribution and Floating Pin Assignment for
\emph{T}-type Junction Region},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {155--167},
year = {1999},
url = {https://doi.org/10.1155/1999/12841},
doi = {10.1155/1999/12841},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Yan99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Yan99a,
author = {Jin{-}Tai Yan},
title = {An {ILP} Formulation for Minimizing the Number of Feedthrough Cells
in a Standard Cell Placement},
journal = {{VLSI} Design},
volume = {10},
number = {2},
pages = {169--176},
year = {1999},
url = {https://doi.org/10.1155/1999/59138},
doi = {10.1155/1999/59138},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Yan99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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