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@article{DBLP:journals/tvlsi/AraujoCAP00, author = {Guido Araujo and Paulo Centoducatte and Rodolfo Azevedo and Ricardo Pannain}, title = {Expression-tree-based algorithms for code compression on embedded {RISC} architectures}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {530--533}, year = {2000}, url = {https://doi.org/10.1109/92.894158}, doi = {10.1109/92.894158}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/AraujoCAP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BellasHP00, author = {Nikolaos Bellas and Ibrahim N. Hajj and Constantine D. Polychronopoulos}, title = {Using dynamic cache management techniques to reduce energy in general purpose processors}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {693--708}, year = {2000}, url = {https://doi.org/10.1109/92.902264}, doi = {10.1109/92.902264}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/BellasHP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BellasHPS00, author = {Nikolaos Bellas and Ibrahim N. Hajj and Constantine D. Polychronopoulos and George I. Stamoulis}, title = {Architectural and compiler techniques for energy reduction in high-performance microprocessors}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {317--326}, year = {2000}, url = {https://doi.org/10.1109/92.845897}, doi = {10.1109/92.845897}, timestamp = {Tue, 22 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/BellasHPS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BeniniBM00, author = {Luca Benini and Alessandro Bogliolo and Giovanni De Micheli}, title = {A survey of design techniques for system-level dynamic power management}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {299--316}, year = {2000}, url = {https://doi.org/10.1109/92.845896}, doi = {10.1109/92.845896}, timestamp = {Mon, 15 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/BeniniBM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BeniniMMMPS00, author = {Luca Benini and Giovanni De Micheli and Alberto Macii and Enrico Macii and Massimo Poncino and Riccardo Scarsi}, title = {Glitch power minimization by selective gate freezing}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {287--298}, year = {2000}, url = {https://doi.org/10.1109/92.845895}, doi = {10.1109/92.845895}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/BeniniMMMPS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BhatiaH00, author = {Dinesh Bhatia and James Haralambides}, title = {Resource requirements and layouts for field programmable interconnection chips}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {346--355}, year = {2000}, url = {https://doi.org/10.1109/92.845901}, doi = {10.1109/92.845901}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/BhatiaH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BhavnagarwalaABM00, author = {Azeez J. Bhavnagarwala and Blanca Austin and Keith A. Bowman and James D. Meindl}, title = {A minimum total power methodology for projecting limits on {CMOS} {GSI}}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {235--251}, year = {2000}, url = {https://doi.org/10.1109/92.845891}, doi = {10.1109/92.845891}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/BhavnagarwalaABM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BlantonH00, author = {Ronald D. Blanton and John P. Hayes}, title = {On the design of fast, easily testable ALU's}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {220--223}, year = {2000}, url = {https://doi.org/10.1109/92.831442}, doi = {10.1109/92.831442}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/BlantonH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BoglioloFD00, author = {Alessandro Bogliolo and Michele Favalli and Maurizio Damiani}, title = {Enabling testability of fault-tolerant circuits by means of I\({}_{\mbox{DDQ}}\)-checkable voters}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {415--419}, year = {2000}, url = {https://doi.org/10.1109/92.863620}, doi = {10.1109/92.863620}, timestamp = {Mon, 15 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/BoglioloFD00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BolchiniMSS00, author = {Cristiana Bolchini and R. Montandon and Fabio Salice and Donatella Sciuto}, title = {Design of VHDL-based totally self-checking finite-state machine and data-path descriptions}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {98--103}, year = {2000}, url = {https://doi.org/10.1109/92.820766}, doi = {10.1109/92.820766}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/BolchiniMSS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/BorrioneDP00, author = {Dominique Borrione and Julia Dushina and Laurence V. Pierre}, title = {A compositional model for the functional verification of high-level synthesis results}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {526--530}, year = {2000}, url = {https://doi.org/10.1109/92.894157}, doi = {10.1109/92.894157}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/BorrioneDP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/CaignetDS00, author = {Fabrice Caignet and S. D.{-}B. Dhia and Etienne Sicard}, title = {On the measurement of crosstalk in integrated circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {606--609}, year = {2000}, url = {https://doi.org/10.1109/92.894165}, doi = {10.1109/92.894165}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/CaignetDS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChaiTWM00, author = {Sek M. Chai and Tarek M. Taha and D. Scott Wills and James D. Meindl}, title = {Heterogeneous architecture models for interconnect-motivated system design}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {660--670}, year = {2000}, url = {https://doi.org/10.1109/92.902260}, doi = {10.1109/92.902260}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChaiTWM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChakrabartyMI00, author = {Krishnendu Chakrabarty and Brian T. Murray and Vikram Iyengar}, title = {Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {633--636}, year = {2000}, url = {https://doi.org/10.1109/92.894170}, doi = {10.1109/92.894170}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabartyMI00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChakrabortyAB00, author = {Tapan J. Chakraborty and Vishwani D. Agrawal and Michael L. Bushnell}, title = {Path delay fault simulation of sequential circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {223--228}, year = {2000}, url = {https://doi.org/10.1109/92.831443}, doi = {10.1109/92.831443}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyAB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChakrabortyAB00a, author = {Tapan J. Chakraborty and Vishwani D. Agrawal and Michael L. Bushnell}, title = {Improving path delay testability of sequential circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {736--741}, year = {2000}, url = {https://doi.org/10.1109/92.902268}, doi = {10.1109/92.902268}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyAB00a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChattopadhyayASP00, author = {Santanu Chattopadhyay and Shelly Adhikari and Sabyasachi Sengupta and Mahua Pal}, title = {Highly regular, modular, and cascadable design of cellular automata-based pattern classifier}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {724--735}, year = {2000}, url = {https://doi.org/10.1109/92.902267}, doi = {10.1109/92.902267}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChattopadhyayASP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChenDZM00, author = {Qiang Chen and Jeffrey A. Davis and Payman Zarkesh{-}Ha and James D. Meindl}, title = {A compact physical via blockage model}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {689--692}, year = {2000}, url = {https://doi.org/10.1109/92.902263}, doi = {10.1109/92.902263}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChenDZM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChenL00, author = {Oscal T.{-}C. Chen and Wei{-}Lung Liu}, title = {An {FIR} processor with programmable dynamic data ranges}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {440--446}, year = {2000}, url = {https://doi.org/10.1109/92.863625}, doi = {10.1109/92.863625}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChenL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChenP00, author = {Song Chen and Adam Postula}, title = {Synthesis of custom interleaved memory systems}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {74--83}, year = {2000}, url = {https://doi.org/10.1109/92.820763}, doi = {10.1109/92.820763}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChenP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/Christie00, author = {Phillip Christie}, title = {Rent exponent prediction methods}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {679--688}, year = {2000}, url = {https://doi.org/10.1109/92.902262}, doi = {10.1109/92.902262}, timestamp = {Mon, 13 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/Christie00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChristieS00, author = {Phillip Christie and Dirk Stroobandt}, title = {The interpretation and application of Rent's rule}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {639--648}, year = {2000}, url = {https://doi.org/10.1109/92.902258}, doi = {10.1109/92.902258}, timestamp = {Mon, 13 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/ChristieS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ConteMST00, author = {Thomas M. Conte and Kishore N. Menezes and Sumedh W. Sathaye and Mark C. Toburen}, title = {System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {129--137}, year = {2000}, url = {https://doi.org/10.1109/92.831433}, doi = {10.1109/92.831433}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ConteMST00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/CorsonelloPC00, author = {Pasquale Corsonello and Stefania Perri and G. Cororullo}, title = {Area-time-power tradeoff in cellular arrays {VLSI} implementations}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {614--624}, year = {2000}, url = {https://doi.org/10.1109/92.894167}, doi = {10.1109/92.894167}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/CorsonelloPC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/CoumeriT00, author = {Sari L. Coumeri and Donald E. Thomas}, title = {Memory modeling for system synthesis}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {327--334}, year = {2000}, url = {https://doi.org/10.1109/92.845898}, doi = {10.1109/92.845898}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/CoumeriT00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/DancyAC00, author = {Abram P. Dancy and Rajeevan Amirtharajah and Anantha P. Chandrakasan}, title = {High-efficiency multiple-output {DC-DC} conversion for low-voltage systems}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {252--263}, year = {2000}, url = {https://doi.org/10.1109/92.845892}, doi = {10.1109/92.845892}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/DancyAC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/DingHP00, author = {Chih{-}Shun Ding and Cheng{-}Ta Hsieh and Massoud Pedram}, title = {Improving the efficiency of Monte Carlo power estimation {[VLSI]}}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {584--593}, year = {2000}, url = {https://doi.org/10.1109/92.894163}, doi = {10.1109/92.894163}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/DingHP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ElesDPP00, author = {Petru Eles and Alex Doboli and Paul Pop and Zebo Peng}, title = {Scheduling with bus access optimization for distributed embedded systems}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {472--491}, year = {2000}, url = {https://doi.org/10.1109/92.894152}, doi = {10.1109/92.894152}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ElesDPP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/FallahLD00, author = {Farzan Fallah and Stan Y. Liao and Srinivas Devadas}, title = {Solving covering problems using LPR-based lower bounds}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {9--17}, year = {2000}, url = {https://doi.org/10.1109/92.820757}, doi = {10.1109/92.820757}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/FallahLD00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/GaylesKOI00, author = {Eric Gayles and Thomas P. Kelliher and Robert Michael Owens and Mary Jane Irwin}, title = {The design of the {MGAP-2:} a micro-grained massively parallel array}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {709--716}, year = {2000}, url = {https://doi.org/10.1109/92.902265}, doi = {10.1109/92.902265}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/GaylesKOI00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/GuptaN00, author = {Subodh Gupta and Farid N. Najm}, title = {Power modeling for high-level power estimation}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {18--29}, year = {2000}, url = {https://doi.org/10.1109/92.820758}, doi = {10.1109/92.820758}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/GuptaN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HamiltonO00, author = {Samuel Norman Hamilton and Alex Orailoglu}, title = {On-line test for fault-secure fault identification}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {446--452}, year = {2000}, url = {https://doi.org/10.1109/92.863626}, doi = {10.1109/92.863626}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/HamiltonO00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HauckHF00, author = {Scott Hauck and Matthew M. Hosler and Thomas W. Fry}, title = {High-performance carry chains for FPGA's}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {138--147}, year = {2000}, url = {https://doi.org/10.1109/92.831434}, doi = {10.1109/92.831434}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/HauckHF00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HegdeS00, author = {Rajamohana Hegde and Naresh R. Shanbhag}, title = {Toward achieving energy efficiency in presence of deep submicron noise}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {379--391}, year = {2000}, url = {https://doi.org/10.1109/92.863617}, doi = {10.1109/92.863617}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/HegdeS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HongTW00, author = {Jin{-}Hua Hong and Chung{-}Hung Tsai and Cheng{-}Wen Wu}, title = {Hierarchical system test by an {IEEE} 1149.5 MTM-bus slave-module interface core}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {503--516}, year = {2000}, url = {https://doi.org/10.1109/92.894154}, doi = {10.1109/92.894154}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/HongTW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HsiaoRP00, author = {Michael S. Hsiao and Elizabeth M. Rudnick and Janak H. Patel}, title = {Peak power estimation of {VLSI} circuits: new peak power measures}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {435--439}, year = {2000}, url = {https://doi.org/10.1109/92.863624}, doi = {10.1109/92.863624}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/HsiaoRP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HuangJS00, author = {Juinn{-}Dar Huang and Jing{-}Yang Jou and Wen{-}Zen Shen}, title = {{ALTO:} an iterative area/performance tradeoff algorithm for LUT-based {FPGA} technology mapping}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {392--400}, year = {2000}, url = {https://doi.org/10.1109/92.863618}, doi = {10.1109/92.863618}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/HuangJS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/HungCS00, author = {Donald L. Hung and Heng{-}Da Cheng and Savang Sengkhamyong}, title = {Design of a configurable accelerator for moment computation}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {741--746}, year = {2000}, url = {https://doi.org/10.1109/92.902269}, doi = {10.1109/92.902269}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/HungCS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/IsmailF00, author = {Yehea I. Ismail and Eby G. Friedman}, title = {Effects of inductance on the propagation delay and repeater insertion in {VLSI} circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {195--206}, year = {2000}, url = {https://doi.org/10.1109/92.831439}, doi = {10.1109/92.831439}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/IsmailF00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/JiangKC00, author = {Yi{-}Min Jiang and Angela Krstic and Kwang{-}Ting Cheng}, title = {Estimation for maximum instantaneous current through supply lines for {CMOS} circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {61--73}, year = {2000}, url = {https://doi.org/10.1109/92.820762}, doi = {10.1109/92.820762}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/JiangKC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/JouCY00, author = {Jer{-}Min Jou and Pei{-}Yin Chen and Sheng{-}Fu Yang}, title = {An adaptive fuzzy logic controller: its {VLSI} architecture and applications}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {52--60}, year = {2000}, url = {https://doi.org/10.1109/92.820761}, doi = {10.1109/92.820761}, timestamp = {Thu, 23 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/JouCY00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/KeshavarziRH00, author = {Ali Keshavarzi and Kaushik Roy and Charles F. Hawkins}, title = {Intrinsic leakage in deep submicron {CMOS} ICs-measurement-based test solutions}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {717--723}, year = {2000}, url = {https://doi.org/10.1109/92.902266}, doi = {10.1109/92.902266}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/KeshavarziRH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/KhalidR00, author = {Mohammed A. S. Khalid and Jonathan Rose}, title = {A novel and efficient routing architecture for multi-FPGA systems}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {30--39}, year = {2000}, url = {https://doi.org/10.1109/92.820759}, doi = {10.1109/92.820759}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/KhalidR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/KimHTY00, author = {Han Bin Kim and Dong Sam Ha and Takeshi Takahashi and Takahiro J. Yamaguchi}, title = {A new approach to built-in self-testable datapath synthesis based on integer linear programming}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {594--605}, year = {2000}, url = {https://doi.org/10.1109/92.894164}, doi = {10.1109/92.894164}, timestamp = {Wed, 08 Feb 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/KimHTY00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/KinnimentYG00, author = {David Kinniment and Alexandre Yakovlev and B. Gao}, title = {Synchronous and asynchronous {A-D} conversion}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {217--220}, year = {2000}, url = {https://doi.org/10.1109/92.831441}, doi = {10.1109/92.831441}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/KinnimentYG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/KirovskiPG00, author = {Darko Kirovski and Miodrag Potkonjak and Lisa M. Guerra}, title = {Cut-based functional debugging for programmable systems-on-chip}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {40--51}, year = {2000}, url = {https://doi.org/10.1109/92.820760}, doi = {10.1109/92.820760}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/KirovskiPG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/KoB00, author = {Uming Ko and Poras T. Balsara}, title = {High-performance energy-efficient D-flip-flop circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {94--98}, year = {2000}, url = {https://doi.org/10.1109/92.820765}, doi = {10.1109/92.820765}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/KoB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiG00, author = {Jian Li and Rajesh K. Gupta}, title = {{HDL} presynthesis optimizations using a tabular model}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {369--378}, year = {2000}, url = {https://doi.org/10.1109/92.863616}, doi = {10.1109/92.863616}, timestamp = {Tue, 20 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiL00, author = {Yanbing Li and Miriam Leeser}, title = {HML, a novel hardware description language and its translation to {VHDL}}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {1--8}, year = {2000}, url = {https://doi.org/10.1109/92.820756}, doi = {10.1109/92.820756}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LubaszewskiMKNC00, author = {Marcelo Lubaszewski and Salvador Mir and Vladimir Kolarik and C. Nielsen and Bernard Courtois}, title = {Design of self-checking fully differential circuits and boards}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {113--128}, year = {2000}, url = {https://doi.org/10.1109/92.831432}, doi = {10.1109/92.831432}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LubaszewskiMKNC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MajhiAJP00, author = {Ananta K. Majhi and V. D. Agrawak and James Jacob and Lalit M. Patnaik}, title = {Line coverage of path delay faults}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {610--614}, year = {2000}, url = {https://doi.org/10.1109/92.894166}, doi = {10.1109/92.894166}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/MajhiAJP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MaksimovicONC00, author = {Dragan Maksimovic and Vojin G. Oklobdzija and Borivoje Nikolic and K. Wayne Current}, title = {Clocked {CMOS} adiabatic logic with integrated single-phase power-clock supply}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {460--463}, year = {2000}, url = {https://doi.org/10.1109/92.863629}, doi = {10.1109/92.863629}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/MaksimovicONC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MandalCG00, author = {Chittaranjan A. Mandal and P. P. Chakrabarti and Sujoy Ghose}, title = {{GABIND:} a {GA} approach to allocation and binding for the high-level synthesis of data paths}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {747--750}, year = {2000}, url = {https://doi.org/10.1109/92.902270}, doi = {10.1109/92.902270}, timestamp = {Mon, 07 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/MandalCG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MarculescuMP00, author = {Diana Marculescu and Radu Marculescu and Massoud Pedram}, title = {Theoretical bounds for switching activity analysis in finite-state machines}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {335--339}, year = {2000}, url = {https://doi.org/10.1109/92.845899}, doi = {10.1109/92.845899}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/MarculescuMP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MarquardtBR00, author = {Alexander Marquardt and Vaughn Betz and Jonathan Rose}, title = {Speed and area tradeoffs in cluster-based {FPGA} architectures}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {84--93}, year = {2000}, url = {https://doi.org/10.1109/92.820764}, doi = {10.1109/92.820764}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/MarquardtBR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MiyazakiTMKISTF00, author = {Toshiaki Miyazaki and Atsushi Takahara and Takahiro Murooka and Masaru Katayama and Takaki Ichimori and Kazuhiro Shirakawa and Akihiro Tsutsui and Ken{-}nosuke Fukami}, title = {PROTEUS-Lite project: dedicated to developing a telecommunication-oriented {FPGA} and its applications}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {401--414}, year = {2000}, url = {https://doi.org/10.1109/92.863619}, doi = {10.1109/92.863619}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/MiyazakiTMKISTF00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/NguyenC00, author = {H. T. Nguyen and A. Chattejee}, title = {Number-splitting with shift-and-add decomposition for power and hardware optimization in linear {DSP} synthesis}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {419--424}, year = {2000}, url = {https://doi.org/10.1109/92.863621}, doi = {10.1109/92.863621}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/NguyenC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/NouraniP00, author = {Mehrdad Nourani and Christos A. Papachristou}, title = {Stability-based algorithms for high-level synthesis of digital ASICs}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {431--435}, year = {2000}, url = {https://doi.org/10.1109/92.863623}, doi = {10.1109/92.863623}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/NouraniP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ObergKH00, author = {Johnny {\"{O}}berg and Anshul Kumar and Ahmed Hemani}, title = {Grammar-based hardware synthesis from port-size independent specifications}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {184--194}, year = {2000}, url = {https://doi.org/10.1109/92.831438}, doi = {10.1109/92.831438}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ObergKH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/PachaABGBPTG00, author = {Christian Pacha and Uwe Auer and Christian Burwick and Peter Gl{\"{o}}sek{\"{o}}tter and Andreas Brennemann and Werner Prost and Franz{-}Josef Tegude and Karl F. Goser}, title = {Threshold logic circuit design of parallel adders using resonant tunneling devices}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {558--572}, year = {2000}, url = {https://doi.org/10.1109/92.894161}, doi = {10.1109/92.894161}, timestamp = {Tue, 21 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/PachaABGBPTG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/Pihl00, author = {Johnny Pihl}, title = {Design automation with the {TSPC} circuit technique: a high-performance wave digital filter}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {456--460}, year = {2000}, url = {https://doi.org/10.1109/92.863628}, doi = {10.1109/92.863628}, timestamp = {Thu, 25 Aug 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/Pihl00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/RahmanR00, author = {Arifur Rahman and Rafael Reif}, title = {System-level performance evaluation of three-dimensional integrated circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {671--678}, year = {2000}, url = {https://doi.org/10.1109/92.902261}, doi = {10.1109/92.902261}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/RahmanR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/RoyL00, author = {Kaushik Roy and D. T. Lee}, title = {Guest editorial: low-power electronics and design}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {233--234}, year = {2000}, url = {https://doi.org/10.1109/TVLSI.2000.845890}, doi = {10.1109/TVLSI.2000.845890}, timestamp = {Sun, 11 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/RoyL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SatyanarayanaP00, author = {Janardhan H. Satyanarayana and Keshab K. Parhi}, title = {Theoretical analysis of word-level switching activity in the presence of glitching and correlation}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {148--159}, year = {2000}, url = {https://doi.org/10.1109/92.831435}, doi = {10.1109/92.831435}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SatyanarayanaP00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ShaerAL00, author = {Bassam Shaer and Sami A. Al{-}Arian and David L. Landis}, title = {Partitioning sequential circuits for pseudoexhaustive testing}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {534--541}, year = {2000}, url = {https://doi.org/10.1109/92.894159}, doi = {10.1109/92.894159}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ShaerAL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ShaerLA00, author = {Bassam Shaer and David L. Landis and Sami A. Al{-}Arian}, title = {Partitioning algorithm to enhance pseudoexhaustive testing of digital {VLSI} circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {750--754}, year = {2000}, url = {https://doi.org/10.1109/92.902271}, doi = {10.1109/92.902271}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ShaerLA00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SinghN00, author = {Montek Singh and Steven M. Nowick}, title = {Synthesis for logical initializability of synchronous finite-state machines}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {542--557}, year = {2000}, url = {https://doi.org/10.1109/92.894160}, doi = {10.1109/92.894160}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SinghN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SjogrenM00, author = {Allen E. Sjogren and Chris J. Myers}, title = {Interfacing synchronous and asynchronous modules within a high-speed pipeline}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {573--583}, year = {2000}, url = {https://doi.org/10.1109/92.894162}, doi = {10.1109/92.894162}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SjogrenM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SongPKN00, author = {Leilei Song and Keshab K. Parhi and Ichiro Kuroda and Takao Nishitani}, title = {Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {160--172}, year = {2000}, url = {https://doi.org/10.1109/92.831436}, doi = {10.1109/92.831436}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SongPKN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/StrolloNC00, author = {Antonio G. M. Strollo and Ettore Napoli and Carlo Cimino}, title = {Analysis of power dissipation in double edge-triggered flip-flops}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {624--629}, year = {2000}, url = {https://doi.org/10.1109/92.894168}, doi = {10.1109/92.894168}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/StrolloNC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SungH00, author = {Wonyong Sung and Soonhoi Ha}, title = {Memory efficient software synthesis with mixed coding style from dataflow graphs}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {522--526}, year = {2000}, url = {https://doi.org/10.1109/92.894156}, doi = {10.1109/92.894156}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SungH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/TongNR00, author = {J. Y. F. Tong and David Nagle and Rob A. Rutenbar}, title = {Reducing power by optimizing the necessary precision/range of floating-point arithmetic}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {273--286}, year = {2000}, url = {https://doi.org/10.1109/92.845894}, doi = {10.1109/92.845894}, timestamp = {Fri, 22 Mar 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/TongNR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/TsaiSW00, author = {Wei{-}Chang Tsai and C. Bernard Shung and Sheng{-}Jyh Wang}, title = {Two systolic architectures for modular multiplication}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {1}, pages = {103--107}, year = {2000}, url = {https://doi.org/10.1109/92.820767}, doi = {10.1109/92.820767}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/TsaiSW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/VermeulenCVM00, author = {Frederik Vermeulen and Francky Catthoor and Diederik Verkest and Hugo De Man}, title = {Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {207--216}, year = {2000}, url = {https://doi.org/10.1109/92.831440}, doi = {10.1109/92.831440}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/VermeulenCVM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/WhiteE00, author = {Brian A. White and Mohamed I. Elmasry}, title = {Low-power design of decimation filters for a digital {IF} receiver}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {339--345}, year = {2000}, url = {https://doi.org/10.1109/92.845900}, doi = {10.1109/92.845900}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/WhiteE00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/WuD00, author = {Allen C.{-}H. Wu and Nikil D. Dutt}, title = {Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98)}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {469--471}, year = {2000}, url = {https://doi.org/10.1109/TVLSI.2000.894151}, doi = {10.1109/TVLSI.2000.894151}, timestamp = {Sat, 05 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/WuD00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YangKNKLLHLHPK00, author = {Jin{-}Hyuk Yang and Byoung{-}Woon Kim and Sang{-}Joon Nam and Young{-}Su Kwon and Dae{-}Hyun Lee and Jong{-}Yeol Lee and Chan{-}Soo Hwang and Yong Hoon Lee and Seung Ho Hwang and In{-}Cheol Park and Chong{-}Min Kyung}, title = {MetaCore: an application-specific programmable {DSP} development system}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {2}, pages = {173--183}, year = {2000}, url = {https://doi.org/10.1109/92.831437}, doi = {10.1109/92.831437}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YangKNKLLHLHPK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YeeS00, author = {Gin Yee and Carl Sechen}, title = {Clock-delayed domino for dynamic circuit design}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {425--430}, year = {2000}, url = {https://doi.org/10.1109/92.863622}, doi = {10.1109/92.863622}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YeeS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YehK00, author = {Chingwei Yeh and Yin{-}Shuin Kang}, title = {Cell-based layout techniques supporting gate-level voltage scaling for low power}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {629--633}, year = {2000}, url = {https://doi.org/10.1109/92.894169}, doi = {10.1109/92.894169}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YehK00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YooCH00, author = {Sungjoo Yoo and Kiyoung Choi and Dong Sam Ha}, title = {Performance improvement of geographically distributed cosimulation by hierarchically grouped messages}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {492--502}, year = {2000}, url = {https://doi.org/10.1109/92.894153}, doi = {10.1109/92.894153}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YooCH00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YunJFCC00, author = {Kenneth Y. Yun and Kevin W. James and Robert H. Fairlie{-}Cuninghame and Supratik Chakraborty and Rene L. Cruz}, title = {A self-timed real-time sorting network}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {356--363}, year = {2000}, url = {https://doi.org/10.1109/92.845903}, doi = {10.1109/92.845903}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YunJFCC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/Zarkesh-HaDM00, author = {Payman Zarkesh{-}Ha and Jeffrey A. Davis and James D. Meindl}, title = {Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {6}, pages = {649--659}, year = {2000}, url = {https://doi.org/10.1109/92.902259}, doi = {10.1109/92.902259}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/Zarkesh-HaDM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ZhangGR00, author = {Hui Zhang and George Varghese and Jan M. Rabaey}, title = {Low-swing on-chip signaling techniques: effectiveness and robustness}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {3}, pages = {264--272}, year = {2000}, url = {https://doi.org/10.1109/92.845893}, doi = {10.1109/92.845893}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ZhangGR00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ZhaoM00, author = {Ying Zhao and Sharad Malik}, title = {Exact memory size estimation for array computations}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {5}, pages = {517--521}, year = {2000}, url = {https://doi.org/10.1109/92.894155}, doi = {10.1109/92.894155}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ZitzlerTB00, author = {Eckart Zitzler and J{\"{u}}rgen Teich and Shuvra S. Bhattacharyya}, title = {Evolutionary algorithms for the synthesis of embedded software}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {8}, number = {4}, pages = {452--455}, year = {2000}, url = {https://doi.org/10.1109/92.863627}, doi = {10.1109/92.863627}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ZitzlerTB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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