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@article{DBLP:journals/tvlsi/0001CUM17,
author = {Yan Zhu and
Chi{-}Hang Chan and
Seng{-}Pan U and
Rui Paulo Martins},
title = {A 10-bit 500-MS/s Partial-Interleaving Pipelined {SAR} {ADC} With
Offset and Reference Mismatch Calibrations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {354--363},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2576468},
doi = {10.1109/TVLSI.2016.2576468},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0001CUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AL-TamimiE17,
author = {Karama M. AL{-}Tamimi and
Kamal El{-}Sankary},
title = {Preweighted Linearized {VCO} Analog-to-Digital Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1983--1987},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2661754},
doi = {10.1109/TVLSI.2017.2661754},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AL-TamimiE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbbasFCT17,
author = {Syed Mohsin Abbas and
YouZhe Fan and
Ji Chen and
Chi{-}Ying Tsui},
title = {High-Throughput and Energy-Efficient Belief Propagation Polar Code
Decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1098--1111},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2620998},
doi = {10.1109/TVLSI.2016.2620998},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbbasFCT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Abdel-HafeezG17,
author = {Saleh Abdel{-}Hafeez and
Ann Gordon{-}Ross},
title = {An Efficient {O(N)} Comparison-Free Sorting Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1930--1942},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2661746},
doi = {10.1109/TVLSI.2017.2661746},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Abdel-HafeezG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbolmaaliMKAP17,
author = {Sheis Abolma'ali and
Nika Mansouri{-}Ghiasi and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Efficient Critical Path Identification Based on Viability Analysis
Method Considering Process Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2668--2672},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2703623},
doi = {10.1109/TVLSI.2017.2703623},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbolmaaliMKAP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AceroFLMMPRRTZ17,
author = {Cesar Acero and
Derek Feltham and
Yingdi Liu and
Elham K. Moghaddam and
Nilanjan Mukherjee and
Marek Patyra and
Janusz Rajski and
Sudhakar M. Reddy and
Jerzy Tyszer and
Justyna Zawada},
title = {Embedded Deterministic Test Points},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2949--2961},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2717844},
doi = {10.1109/TVLSI.2017.2717844},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AceroFLMMPRRTZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AdapaBBRAM17,
author = {Bhagyaraja Adapa and
Dwaipayan Biswas and
Swati Bhardwaj and
Shashank Raghuraman and
Amit Acharyya and
Koushik Maharatna},
title = {Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1568--1572},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2633543},
doi = {10.1109/TVLSI.2016.2633543},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AdapaBBRAM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AgboTKHKWRC17,
author = {Innocent Agbo and
Mottaqiallah Taouil and
Daniel Kraak and
Said Hamdioui and
Halil Kukner and
Pieter Weckx and
Praveen Raghavan and
Francky Catthoor},
title = {Integral Impact of BTI, {PVT} Variation, and Workload on {SRAM} Sense
Amplifier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1444--1454},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2643618},
doi = {10.1109/TVLSI.2016.2643618},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AgboTKHKWRC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AghaieKA17,
author = {Anita Aghaie and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked
on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1528--1536},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2633412},
doi = {10.1109/TVLSI.2016.2633412},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AghaieKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmedPB17,
author = {Ali Ahmed and
Kyungbae Park and
Sanghyeon Baeg},
title = {Resource-Efficient SRAM-Based Ternary Content Addressable Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1583--1587},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2636294},
doi = {10.1109/TVLSI.2016.2636294},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmedPB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmedRF17,
author = {Khaled E. Ahmed and
Mohamed R. M. Rizk and
Mohammed M. Farag},
title = {Overloaded {CDMA} Crossbar for Network-On-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1842--1855},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2664660},
doi = {10.1109/TVLSI.2017.2664660},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmedRF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AkbariKAP17,
author = {Omid Akbari and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable
Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1352--1361},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2643003},
doi = {10.1109/TVLSI.2016.2643003},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AkbariKAP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlamehN17,
author = {Abdul Hafiz Alameh and
Frederic Nabki},
title = {A 0.13-{\(\mathrm{\mu}\)}m {CMOS} Dynamically Reconfigurable Charge
Pump for Electrostatic {MEMS} Actuation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1261--1270},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2629439},
doi = {10.1109/TVLSI.2016.2629439},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlamehN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Algueta-MiguelR17,
author = {Jos{\'{e}} Mar{\'{\i}}a Algueta{-}Miguel and
Jaime Ram{\'{\i}}rez{-}Angulo and
Enrique Mirazo and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal},
title = {A Simple Miller Compensation With Essential Bandwidth Improvement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3186--3192},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2733082},
doi = {10.1109/TVLSI.2017.2733082},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Algueta-MiguelR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlhasssanZS17,
author = {Nashiru Alhassan and
Zekun Zhou and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {An All-MOSFET Sub-1-V Voltage Reference With a - 51 -dB {PSR} up to
60 MHz},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {919--928},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2614438},
doi = {10.1109/TVLSI.2016.2614438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlhasssanZS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AmanollahiJ17,
author = {Saba Amanollahi and
Ghassem Jaberipur},
title = {Energy-Efficient {VLSI} Realization of Binary64 Division With Redundant
Number Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {954--961},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2604346},
doi = {10.1109/TVLSI.2016.2604346},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AmanollahiJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AppeltansRKFPD17,
author = {Raf Appeltans and
Praveen Raghavan and
Gouri Sankar Kar and
Arnaud Furn{\'{e}}mont and
Liesbet Van der Perre and
Wim Dehaene},
title = {A Smaller, Faster, and More Energy-Efficient Complementary {STT-MRAM}
Cell Uses Three Transistors and a Ground Grid: More Is Actually Less},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1204--1214},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2633004},
doi = {10.1109/TVLSI.2016.2633004},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AppeltansRKFPD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ArdakaniLOHG17,
author = {Arash Ardakani and
Fran{\c{c}}ois Leduc{-}Primeau and
Naoya Onizawa and
Takahiro Hanyu and
Warren J. Gross},
title = {{VLSI} Implementation of Deep Neural Network Using Integral Stochastic
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2688--2699},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2654298},
doi = {10.1109/TVLSI.2017.2654298},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ArdakaniLOHG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AslamKG17,
author = {Chaudhry Adnan Aslam and
Kui Cai and
Yong Liang Guan},
title = {Mitigating Stuck Cell Failures in {MLC} {NAND} Flash Memory via Inferred
Erasure Decoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2285--2295},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2683536},
doi = {10.1109/TVLSI.2017.2683536},
timestamp = {Sat, 17 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AslamKG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AungYTK17,
author = {Myat Thu Linn Aung and
Takefumi Yoshikawa and
Chuan Seng Tan and
Tony Tae{-}Hyoung Kim},
title = {Yield Enhancement of Face-to-Face Cu-Cu Bonding With Dual-Mode Transceivers
in 3DICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1023--1031},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2623659},
doi = {10.1109/TVLSI.2016.2623659},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AungYTK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AurangozebHNSH17,
author = {Aurangozeb and
A. K. M. Delwar Hossain and
Can Ni and
Quazi Sharar and
Masum Hossain},
title = {Time-Domain Arithmetic Logic Unit With Built-In Interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2828--2841},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2724600},
doi = {10.1109/TVLSI.2017.2724600},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AurangozebHNSH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AwadTTK17,
author = {Ahmed Awad and
Atsushi Takahashi and
Satoshi Tanaka and
Chikaaki Kodama},
title = {A Fast Process-Variation-Aware Mask Optimization Algorithm With a
Novel Intensity Modeling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {998--1011},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2616840},
doi = {10.1109/TVLSI.2016.2616840},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AwadTTK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AwanoMS17,
author = {Hiromitsu Awano and
Shumpei Morita and
Takashi Sato},
title = {Scalable Device Array for Statistical Characterization of BTI-Related
Parameters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1455--1466},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2638021},
doi = {10.1109/TVLSI.2016.2638021},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AwanoMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzarkhishPRLB17,
author = {Erfan Azarkhish and
Christoph Pfister and
Davide Rossi and
Igor Loi and
Luca Benini},
title = {Logic-Base Interconnect Design for Near Memory Computing in the Smart
Memory Cube},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {210--223},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2570283},
doi = {10.1109/TVLSI.2016.2570283},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AzarkhishPRLB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzrielGGM17,
author = {Leonid Azriel and
Ran Ginosar and
Shay Gueron and
Avi Mendelson},
title = {Using Scan Side Channel to Detect {IP} Theft},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3268--3280},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2715188},
doi = {10.1109/TVLSI.2017.2715188},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AzrielGGM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaK17,
author = {Ngoc Le Ba and
Tony Tae{-}Hyoung Kim},
title = {Design of Temperature-Aware Low-Voltage 8T {SRAM} in {SOI} Technology
for High-Temperature Operation {(25} {\%}C-300 {\%}C)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2383--2387},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2686600},
doi = {10.1109/TVLSI.2017.2686600},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaeNJ17,
author = {Woo{-}Rham Bae and
Borivoje Nikolic and
Deog{-}Kyoon Jeong},
title = {Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative
to Group Delay Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3543--3547},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2747157},
doi = {10.1109/TVLSI.2017.2747157},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaeNJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaekCS17,
author = {Donkyu Baek and
Naehyuck Chang and
Donghwa Shin},
title = {Compressed On-Chip Framebuffer Cache for Low-Power Display Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1215--1223},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2636849},
doi = {10.1109/TVLSI.2016.2636849},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaekCS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaiKS17,
author = {Xiaoyin Bai and
Zhi{-}Hui Kong and
Liter Siek},
title = {A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time
Delay Control for Wireless Power Transmission},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1297--1306},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2626301},
doi = {10.1109/TVLSI.2016.2626301},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaiKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BambergO17,
author = {Lennart Bamberg and
Alberto Garc{\'{\i}}a Ortiz},
title = {High-Level Energy Estimation for Submicrometric {TSV} Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2856--2866},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2713601},
doi = {10.1109/TVLSI.2017.2713601},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BambergO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaoRTMVTW17,
author = {Trong Huynh Bao and
Julien Ryckaert and
Zsolt Tokei and
Abdelkarim Mercha and
Diederik Verkest and
Aaron Voon{-}Yew Thean and
Piet Wambacq},
title = {Statistical Timing Analysis Considering Device and Interconnect Variability
for {BEOL} Requirements in the 5-nm Node and Beyond},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1669--1680},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2647853},
doi = {10.1109/TVLSI.2017.2647853},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaoRTMVTW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BasuSCR17,
author = {Prabal Basu and
Rajesh Jayashankara Shridevi and
Koushik Chakraborty and
Sanghamitra Roy},
title = {IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through
Flow-Control and Routing Algorithms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2035--2044},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2673808},
doi = {10.1109/TVLSI.2017.2673808},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BasuSCR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhagavatulaJ17,
author = {Srikar Bhagavatula and
Byunghoo Jung},
title = {Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained
Power Management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {416--426},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2588322},
doi = {10.1109/TVLSI.2016.2588322},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhagavatulaJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhamraLWI17,
author = {Hansraj Bhamra and
John Lynch and
Matthew Ward and
Pedro P. Irazoqui},
title = {A Noise-Power-Area Optimized Biosensing Front End for Wireless Body
Sensor Nodes and Medical Implantable Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2917--2928},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2714171},
doi = {10.1109/TVLSI.2017.2714171},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhamraLWI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BiMWL17,
author = {Xiuyuan Bi and
Mengjie Mao and
Danghui Wang and
Hai Helen Li},
title = {Cross-Layer Optimization for Multilevel Cell {STT-RAM} Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1807--1820},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2665543},
doi = {10.1109/TVLSI.2017.2665543},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BiMWL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BishnoiOT17,
author = {Rajendra Bishnoi and
Fabian Oboril and
Mehdi Baradaran Tahoori},
title = {Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1421--1432},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2630315},
doi = {10.1109/TVLSI.2016.2630315},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BishnoiOT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BiswasMPMAKJO17,
author = {Dwaipayan Biswas and
Koushik Maharatna and
Goran Panic and
Evangelos B. Mazomenos and
Josy Achner and
Jasmin Klemke and
Michael J{\"{o}}bges and
Steffen Ortmann},
title = {Low-Complexity Framework for Movement Classification Using Body-Worn
Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1537--1548},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2641046},
doi = {10.1109/TVLSI.2016.2641046},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BiswasMPMAKJO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BlutmanFKKLG17,
author = {Kristof Blutman and
Hamed Fatemi and
Ajay Kapoor and
Andrew B. Kahng and
Jiajia Li and
Jos{\'{e}} Pineda de Gyvez},
title = {Logic Design Partitioning for Stacked Power Domains},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3045--3056},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2729587},
doi = {10.1109/TVLSI.2017.2729587},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BlutmanFKKLG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BodhePAV17,
author = {Shraddha Bodhe and
Irith Pomeranz and
M. Enamul Amyeen and
Srikanth Venkataraman},
title = {Reordering Tests for Efficient Fail Data Collection and Tester Time
Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1497--1505},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2628321},
doi = {10.1109/TVLSI.2016.2628321},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BodhePAV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BoumcheddaNGABT17,
author = {Reda Boumchedda and
Jean{-}Philippe Noel and
Bastien Giraud and
Kaya Can Akyel and
Melanie Brocard and
David Turgis and
Edith Beign{\'{e}}},
title = {High-Density 4T {SRAM} Bitcell in 14-nm 3-D CoolCube Technology Exploiting
Assist Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2296--2306},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2688862},
doi = {10.1109/TVLSI.2017.2688862},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BoumcheddaNGABT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BuiPBBT17,
author = {Duy{-}Hieu Bui and
Diego Puschini and
Simone Bacles{-}Min and
Edith Beign{\'{e}} and
Xuan{-}Tu Tran},
title = {{AES} Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level
Internet-of-Things Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3281--3290},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2716386},
doi = {10.1109/TVLSI.2017.2716386},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BuiPBBT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CairoVTZG17,
author = {Fabrizio Cairo and
Marco Vacca and
Giovanna Turvani and
Maurizio Zamboni and
Mariagrazia Graziano},
title = {Domain Wall Interconnections for {NML}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3067--3076},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2739748},
doi = {10.1109/TVLSI.2017.2739748},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CairoVTZG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoLYYZS17,
author = {Peng Cao and
Bo Liu and
Jinjiang Yang and
Jun Yang and
Meng Zhang and
Longxing Shi},
title = {Context Management Scheme Optimization of Coarse-Grained Reconfigurable
Architecture for Multimedia Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2321--2331},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2695493},
doi = {10.1109/TVLSI.2017.2695493},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoLYYZS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CavalheiroMV17,
author = {David Cavalheiro and
Francesc Moll and
Stanimir Stoyanov Valtchev},
title = {Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy
Harvesting Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {988--997},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2617203},
doi = {10.1109/TVLSI.2016.2617203},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CavalheiroMV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CerqueiraS17,
author = {Joao Pedro Cerqueira and
Mingoo Seok},
title = {Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold
Parallel Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {189--197},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2576280},
doi = {10.1109/TVLSI.2016.2576280},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CerqueiraS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaLM17,
author = {Soonyoung Cha and
Taizhi Liu and
Linda Milor},
title = {Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling
in Circuits With Die-to-Die Calibration Through Power Supply and Ground
Signal Measurements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2271--2284},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2683261},
doi = {10.1109/TVLSI.2017.2683261},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaLM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabartyABBC17,
author = {Krishnendu Chakrabarty and
Massimo Alioto and
Bevan M. Baas and
Chirn Chye Boon and
Meng{-}Fan Chang and
Naehyuck Chang and
Yao{-}Wen Chang and
Chip{-}Hong Chang and
Shih{-}Chieh Chang and
Poki Chen and
Masud H. Chowdhury and
Pasquale Corsonello and
Ibrahim Abe M. Elfadel and
Said Hamdioui and
Masanori Hashimoto and
Tsung{-}Yi Ho and
Houman Homayoun and
Yuh{-}Shyan Hwang and
Rajiv V. Joshi and
Tanay Karnik and
Mehran Mozaffari Kermani and
Chulwoo Kim and
Tae{-}Hyoung Kim and
Jaydeep P. Kulkarni and
Eren Kursun and
Erik Larsson and
Hai (Helen) Li and
Huawei Li and
Patrick P. Mercier and
Prabhat Mishra and
Makoto Nagata and
Arun S. Natarajan and
Koji Nii and
Partha Pratim Pande and
Ioannis Savidis and
Mingoo Seok and
Sheldon X.{-}D. Tan and
Mark M. Tehranipoor and
Aida Todri{-}Sanial and
Miroslav N. Velev and
Xiaoqing Wen and
Jiang Xu and
Wei Zhang and
Zhengya Zhang and
Stacey Weber Jackson},
title = {Editorial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {1--20},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2638578},
doi = {10.1109/TVLSI.2016.2638578},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabartyABBC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabartyAJ17,
author = {Krishnendu Chakrabarty and
Massimo Alioto and
Rajiv V. Joshi},
title = {Editorial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2393},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2737278},
doi = {10.1109/TVLSI.2017.2737278},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabartyAJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChandranPSBCK17,
author = {Sandeep Chandran and
Preeti Ranjan Panda and
Smruti R. Sarangi and
Ayan Bhattacharyya and
Deepak Chauhan and
Sharad Kumar},
title = {Managing Trace Summaries to Minimize Stalls During Postsilicon Validation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1881--1894},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2657604},
doi = {10.1109/TVLSI.2017.2657604},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChandranPSBCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangASCYL17,
author = {Kyungwook Chang and
Kartik Acharya and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Impact and Design Guideline of Monolithic 3-D {IC} at the 7-nm Technology
Node},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2118--2129},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2686426},
doi = {10.1109/TVLSI.2017.2686426},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangASCYL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaoLCHT17,
author = {I{-}Jen Chao and
Bin{-}Da Liu and
Soon{-}Jyh Chang and
Chun{-}Yueh Huang and
Hsin{-}Wen Ting},
title = {Analyses of Splittable Amplifier Technique and Cancellation of Memory
Effect for Opamp Sharing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {621--634},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2586184},
doi = {10.1109/TVLSI.2016.2586184},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaoLCHT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CheahMBK17,
author = {Michael Cheah and
Debashis Mandal and
Bertan Bakkaloglu and
Sayfe Kiaei},
title = {A 100-mA, 99.11{\%} Current Efficiency, 2-mV\({}_{\mbox{pp}}\) Ripple
Digitally Controlled {LDO} With Active Ripple Suppression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {696--704},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2596708},
doi = {10.1109/TVLSI.2016.2596708},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CheahMBK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenBKAX17,
author = {Pingxiuqi Chen and
Shaik Nazeem Basha and
Mehran Mozaffari Kermani and
Reza Azarderakhsh and
Jiafeng Xie},
title = {{FPGA} Realization of Low Register Systolic All-One-Polynomial Multipliers
Over {\textdollar}GF(2\{m\}){\textdollar} and Their Applications in
Trinomial Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {725--734},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2600568},
doi = {10.1109/TVLSI.2016.2600568},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenBKAX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHCTL17,
author = {Poki Chen and
Ya{-}Yun Hsiao and
Yi{-}Su Chung and
Wei Xiang Tsai and
Jhih{-}Min Lin},
title = {A 2.5-ps Bin Size and 6.7-ps Resolution {FPGA} Time-to-Digital Converter
Based on Delay Wrapping and Averaging},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {114--124},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2569626},
doi = {10.1109/TVLSI.2016.2569626},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHCTL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenTLWH17,
author = {Yen{-}Hao Chen and
Yi{-}Lun Tang and
Yi{-}Yu Liu and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling
Mechanism for Reliability Enhancements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {820--832},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2614993},
doi = {10.1109/TVLSI.2016.2614993},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenTLWH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWZMDC17,
author = {Shuai Chen and
Luke Wang and
Hong Zhang and
Rosanah Murugesu and
Dustin Dunwell and
Anthony Chan Carusone},
title = {All-Digital Calibration of Timing Mismatch Error in Time-Interleaved
Analog-to-Digital Converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2552--2560},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2703141},
doi = {10.1109/TVLSI.2017.2703141},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWZMDC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Chiang17,
author = {Cheng{-}Ta Chiang},
title = {Design of a {CMOS} Chlorophyll Concentration Detector Based on Organic
Chlorophyll Battery for Measuring Vegetable Chlorophyll Concentration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1725--1730},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2648639},
doi = {10.1109/TVLSI.2017.2648639},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Chiang17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Cho17,
author = {Je{-}Kwang Cho},
title = {A 92-dB DR, 24.3-mW, 1.25-MHz {BW} Sigma-Delta Modulator Using Dynamically
Biased Op Amp Sharing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {881--893},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2604255},
doi = {10.1109/TVLSI.2016.2604255},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Cho17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoW17,
author = {Je{-}Kwang Cho and
Sunsik Woo},
title = {A 6-mW, 70.1-dB SNDR, and 20-MHz {BW} Continuous-Time Sigma-Delta
Modulator Using Low-Noise High-Linearity Feedback {DAC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1742--1755},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2651055},
doi = {10.1109/TVLSI.2017.2651055},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiBA17,
author = {Jongsok Choi and
Stephen Dean Brown and
Jason Helge Anderson},
title = {From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis
for FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2867--2880},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2720623},
doi = {10.1109/TVLSI.2017.2720623},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiBA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiK17,
author = {Ju Hee Choi and
Jong Wook Kwak},
title = {Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque
{RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1236--1249},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2637897},
doi = {10.1109/TVLSI.2016.2637897},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChongHLGC17,
author = {Kwen{-}Siong Chong and
Weng{-}Geng Ho and
Tong Lin and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Sense Amplifier Half-Buffer {(SAHB)} {A} Low-Power High-Performance
Asynchronous Logic {QDI} Cell Template},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {402--415},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2583118},
doi = {10.1109/TVLSI.2016.2583118},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChongHLGC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChouCLG17,
author = {Pang{-}Yen Chou and
Nai{-}Chen Chen and
Mark Po{-}Hung Lin and
Helmut Graeb},
title = {Matched-Routing Common-Centroid 3-D {MOM} Capacitors for Low-Power
Data Converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2234--2247},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2687980},
doi = {10.1109/TVLSI.2017.2687980},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChouCLG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChungY17,
author = {Yung{-}Hui Chung and
Chia{-}Wei Yen},
title = {An 11-bit 100-MS/s Subranged-SAR {ADC} in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3434--3443},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2742515},
doi = {10.1109/TVLSI.2017.2742515},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChungY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CiprutF17,
author = {Albert Ciprut and
Eby G. Friedman},
title = {Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {286--293},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2570120},
doi = {10.1109/TVLSI.2016.2570120},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CiprutF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CnuddeN17,
author = {Thomas De Cnudde and
Svetla Nikova},
title = {Securing the {PRESENT} Block Cipher Against Combined Side-Channel
Analysis and Fault Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3291--3301},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2713483},
doi = {10.1109/TVLSI.2017.2713483},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CnuddeN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CollettaFSR17,
author = {Gustavo Della Colletta and
Luis Henrique de Carvalho Ferreira and
Sameer R. Sonkusale and
Giseli V. Rocha},
title = {A 20-nW 0.25-V Inverter-Based Asynchronous Delta-Sigma Modulator in
130-nm Digital {CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3455--3463},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2741343},
doi = {10.1109/TVLSI.2017.2741343},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CollettaFSR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CuiCNMJ17,
author = {Xiaole Cui and
Xiaoxin Cui and
Yewen Ni and
Min Miao and
Yufeng Jin},
title = {An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral
System for Through Silicon Vias},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1601--1610},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2651141},
doi = {10.1109/TVLSI.2017.2651141},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CuiCNMJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CuiZH17,
author = {Yingnan Cui and
Wei Zhang and
Bingsheng He},
title = {A Variation-Aware Adaptive Fuzzy Control System for Thermal Management
of Microprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {683--695},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2596338},
doi = {10.1109/TVLSI.2016.2596338},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CuiZH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaiJ17,
author = {Xiaoliang Dai and
Niraj K. Jha},
title = {Improving Convergence and Simulation Time of Quantum Hydrodynamic
Simulation: Application to Extraction of Best 10-nm FinFET Parameter
Values},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {319--329},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2564300},
doi = {10.1109/TVLSI.2016.2564300},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaiJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaiJ17a,
author = {Xiaoliang Dai and
Niraj K. Jha},
title = {Using a Device State Library to Boost the Performance of {TCAD} Mixed-Mode
Simulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2616--2624},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2712804},
doi = {10.1109/TVLSI.2017.2712804},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaiJ17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DamschenBH17,
author = {Marvin Damschen and
Lars Bauer and
J{\"{o}}rg Henkel},
title = {Timing Analysis of Tasks on Runtime Reconfigurable Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {294--307},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2572304},
doi = {10.1109/TVLSI.2016.2572304},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DamschenBH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DangATOA17,
author = {Khanh N. Dang and
Akram Ben Ahmed and
Xuan{-}Tu Tran and
Yuichi Okuyama and
Abderazek Ben Abdallah},
title = {A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip
Using Analytical Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3099--3112},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2736004},
doi = {10.1109/TVLSI.2017.2736004},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DangATOA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaraHT17,
author = {Chandra Babu Dara and
Themistoklis Haniotakis and
Spyros Tragoudas},
title = {Delay Analysis for Current Mode Threshold Logic Gate Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1063--1071},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2608953},
doi = {10.1109/TVLSI.2016.2608953},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaraHT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongYFFBS17,
author = {Qing Dong and
Kaiyuan Yang and
Laura Fick and
David Fick and
David T. Blaauw and
Dennis Sylvester},
title = {Low-Power and Compact Analog-to-Digital Converter Using Spintronic
Racetrack Memory Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {907--918},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2622224},
doi = {10.1109/TVLSI.2016.2622224},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DongYFFBS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuraisamyP17,
author = {Karthi Duraisamy and
Partha Pratim Pande},
title = {Enabling High-Performance {SMART} NoC Architectures Using On-Chip
Wireless Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3495--3508},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2748884},
doi = {10.1109/TVLSI.2017.2748884},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DuraisamyP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuraisamyXBP17,
author = {Karthi Duraisamy and
Yuankun Xue and
Paul Bogdan and
Partha Pratim Pande},
title = {Multicast-Aware High-Performance Wireless Network-on-Chip Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1126--1139},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2612647},
doi = {10.1109/TVLSI.2016.2612647},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DuraisamyXBP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EllaithyEIZZ17,
author = {Dina M. Ellaithy and
Magdy A. El{-}Moursy and
Ghada H. Ibrahim and
Amal Zaki and
Abdelhalim Zekry},
title = {Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2144--2152},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2667714},
doi = {10.1109/TVLSI.2017.2667714},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EllaithyEIZZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErdemYC17,
author = {Serdar S{\"{u}}er Erdem and
Tugrul Yanik and
Anil {\c{C}}elebi},
title = {A General Digit-Serial Architecture for Montgomery Modular Multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1658--1668},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2652979},
doi = {10.1109/TVLSI.2017.2652979},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ErdemYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangW17,
author = {Shao{-}Yun Fang and
Kuo{-}Hao Wu},
title = {Cut Mask Optimization With Wire Planning in Self-Aligned Multiple
Patterning Full-Chip Routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {581--593},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2600681},
doi = {10.1109/TVLSI.2016.2600681},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FarhanNGA17,
author = {Mina A. Farhan and
Michel S. Nakhla and
Emad Gad and
Ramachandra Achar},
title = {Parallel High-Order Envelope-Following Method for Fast Transient Analysis
of Highly Oscillatory Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {261--270},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2566443},
doi = {10.1109/TVLSI.2016.2566443},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FarhanNGA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FarkhaniTPMM17,
author = {Hooman Farkhani and
Mohammad Tohidi and
Ali Peiravi and
Jens Kargaard Madsen and
Farshad Moradi},
title = {{STT-RAM} Energy Reduction Using Self-Referenced Differential Write
Termination Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {476--487},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2588585},
doi = {10.1109/TVLSI.2016.2588585},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FarkhaniTPMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FengL17,
author = {Xiang Feng and
Shuguo Li},
title = {Design of an Area-Effcient Million-Bit Integer Multiplier Using Double
Modulus {NTT}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2658--2662},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2691727},
doi = {10.1109/TVLSI.2017.2691727},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FengL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FirouziFKRB17,
author = {Farshad Firouzi and
Bahar J. Farahani and
Andrew B. Kahng and
Jan M. Rabaey and
Natasha Balac},
title = {Guest Editorial: Alternative Computing and Machine Learning for Internet
of Things},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2685--2687},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2742098},
doi = {10.1109/TVLSI.2017.2742098},
timestamp = {Tue, 31 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FirouziFKRB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FritzF17,
author = {Christopher Fritz and
Adly T. Fam},
title = {Fast Binary Counters Based on Symmetric Stacking},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2971--2975},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2723475},
doi = {10.1109/TVLSI.2017.2723475},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FritzF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuZLX17,
author = {Chenchen Fu and
Yingchao Zhao and
Minming Li and
Chun Jason Xue},
title = {Maximizing Common Idle Time on Multicore Processors With Shared Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2095--2108},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2669973},
doi = {10.1109/TVLSI.2017.2669973},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FuZLX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuketaOM17,
author = {Hiroshi Fuketa and
Shin{-}ichi O'Uchi and
Takashi Matsukawa},
title = {A Closed-Form Expression for Minimum Operating Voltage of {CMOS} {D}
Flip-Flop},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2007--2016},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2677978},
doi = {10.1109/TVLSI.2017.2677978},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FuketaOM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FusellaC17,
author = {Edoardo Fusella and
Alessandro Cilardo},
title = {H\({}^{\mbox{2}}\)ONoC: {A} Hybrid Optical-Electronic NoC Based on
Hybrid Topology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {330--343},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2581486},
doi = {10.1109/TVLSI.2016.2581486},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FusellaC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GalaVRK17,
author = {Neel Gala and
Swagath Venkataramani and
Anand Raghunathan and
V. Kamakoti},
title = {Approximate Error Detection With Stochastic Checkers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2258--2270},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2684816},
doi = {10.1109/TVLSI.2017.2684816},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GalaVRK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Garcia-RedondoR17,
author = {Fernando Garc{\'{\i}}a{-}Redondo and
Pablo Royer and
Marisa L{\'{o}}pez{-}Vallejo and
Hernan Aparicio and
Pablo Ituero and
Carlos A. L{\'{o}}pez{-}Barrio},
title = {Reconfigurable Writing Architecture for Reliable {RRAM} Operation
in Wide Temperature Ranges},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1224--1235},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2634083},
doi = {10.1109/TVLSI.2016.2634083},
timestamp = {Fri, 24 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Garcia-RedondoR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GarridoSVG17,
author = {Mario Garrido and
Miguel Angel S{\'{a}}nchez and
Mar{\'{\i}}a Luisa L{\'{o}}pez Vallejo and
Jes{\'{u}}s Grajal},
title = {A 4096-Point Radix-4 Memory-Based {FFT} Using {DSP} Slices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {375--379},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2567784},
doi = {10.1109/TVLSI.2016.2567784},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GarridoSVG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GautschiSTLPRFG17,
author = {Michael Gautschi and
Pasquale Davide Schiavone and
Andreas Traber and
Igor Loi and
Antonio Pullini and
Davide Rossi and
Eric Flamand and
Frank K. G{\"{u}}rkaynak and
Luca Benini},
title = {Near-Threshold {RISC-V} Core With {DSP} Extensions for Scalable IoT
Endpoint Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2700--2713},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2654506},
doi = {10.1109/TVLSI.2017.2654506},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GautschiSTLPRFG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GinesPR17,
author = {Antonio J. Gin{\'{e}}s and
Eduardo J. Peral{\'{\i}}as and
Adoraci{\'{o}}n Rueda},
title = {Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline
ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2966--2970},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2718625},
doi = {10.1109/TVLSI.2017.2718625},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GinesPR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GitermanAT17,
author = {Robert Giterman and
Lior Atias and
Adam Teman},
title = {Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic
Memory for Space Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {502--509},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2603923},
doi = {10.1109/TVLSI.2016.2603923},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GitermanAT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GluzerW17,
author = {Doron Gluzer and
Shmuel Wimer},
title = {Probability-Driven Multibit Flip-Flop Integration With Clock Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1173--1177},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2614004},
doi = {10.1109/TVLSI.2016.2614004},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GluzerW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GongPCWCW17,
author = {Na Gong and
Seyed Alireza Pourbakhsh and
Xiaowei Chen and
Xin Wang and
Dongliang Chen and
Jinhui Wang},
title = {{SPIDER:} Sizing-Priority-Based Application-Driven Memory for Mobile
Video Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2625--2634},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2715002},
doi = {10.1109/TVLSI.2017.2715002},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GongPCWCW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GorginJ17,
author = {Saeid Gorgin and
Ghassem Jaberipur},
title = {Sign-Magnitude Encoding for Efficient {VLSI} Realization of Decimal
Multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {75--86},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2579667},
doi = {10.1109/TVLSI.2016.2579667},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GorginJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GorjiG17,
author = {Javad Gorji and
M. B. Ghaznavi{-}Ghoushchi},
title = {A Process-Independent and Highly Linear {DCO} for Crowded Heterogeneous
IoT Devices in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3369--3379},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2715167},
doi = {10.1109/TVLSI.2017.2715167},
timestamp = {Thu, 26 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GorjiG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GrudnitskyBH17,
author = {Artjom Grudnitsky and
Lars Bauer and
J{\"{o}}rg Henkel},
title = {Efficient Partial Online Synthesis of Special Instructions for Reconfigurable
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {594--607},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2585603},
doi = {10.1109/TVLSI.2016.2585603},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GrudnitskyBH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuanW17,
author = {Menglong Guan and
Lei Wang},
title = {Improving {DRAM} Performance in 3-D ICs via Temperature Aware Refresh},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {833--843},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2606085},
doi = {10.1109/TVLSI.2016.2606085},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuanW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoDMJ17,
author = {Xiaolong Guo and
Raj Gautam Dutta and
Prabhat Mishra and
Yier Jin},
title = {Automatic Code Converter Enhanced {PCH} Framework for SoC Trust Verification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3390--3400},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2751615},
doi = {10.1109/TVLSI.2017.2751615},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoDMJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoWSC17,
author = {Jie Guo and
Danghui Wang and
Zili Shao and
Yiran Chen},
title = {Data-Pattern-Aware Error Prevention Technique to Improve System Reliability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1433--1443},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2642055},
doi = {10.1109/TVLSI.2016.2642055},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoWSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoZLHLWXM17,
author = {Jing Guo and
Lei Zhu and
Wenyi Liu and
Hai Huang and
Shanshan Liu and
Tianqi Wang and
Liyi Xiao and
Zhigang Mao},
title = {Novel Radiation-Hardened-by-Design {(RHBD)} 12T Memory Cell for Aerospace
Applications in Nanoscale {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1593--1600},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2645282},
doi = {10.1109/TVLSI.2016.2645282},
timestamp = {Sun, 24 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoZLHLWXM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuptaGP17,
author = {Shourya Gupta and
Kirti Gupta and
Neeta Pandey},
title = {A 32-nm Subthreshold 7T {SRAM} Bit Cell With Read Assist},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3473--3483},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2746683},
doi = {10.1109/TVLSI.2017.2746683},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuptaGP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaoNWY17,
author = {Cong Hao and
Jianmo Ni and
Nan Wang and
Takeshi Yoshimura},
title = {Interconnection Allocation Between Functional Units and Registers
in High-Level Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1140--1153},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2607758},
doi = {10.1109/TVLSI.2016.2607758},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HaoNWY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeCTWT17,
author = {Miao Tony He and
Gustavo K. Contreras and
Dat Tran and
LeRoy Winemberg and
Mark M. Tehranipoor},
title = {Test-Point Insertion Efficiency Analysis for {LBIST} in High-Assurance
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2602--2615},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2704104},
doi = {10.1109/TVLSI.2017.2704104},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeCTWT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeZGJ17,
author = {Jiaji He and
Yiqiang Zhao and
Xiaolong Guo and
Yier Jin},
title = {Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel
Statistical Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2939--2948},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2727985},
doi = {10.1109/TVLSI.2017.2727985},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeZGJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hiasat17,
author = {Ahmad A. Hiasat},
title = {A Residue-to-Binary Converter for the Extended Four-Moduli Set \{2\({}^{\mbox{n}}\)-1,
2\({}^{\mbox{n}}\)+1, 2\({}^{\mbox{2n}}\)+1, 2\({}^{\mbox{2n+p}}\)\}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2188--2192},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2681758},
doi = {10.1109/TVLSI.2017.2681758},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hiasat17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoLCK17,
author = {Chien{-}Chung Ho and
Yu{-}Ping Liu and
Yuan{-}Hao Chang and
Tei{-}Wei Kuo},
title = {Antiwear Leveling Design for SSDs With Hybrid {ECC} Capability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {488--501},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2589318},
doi = {10.1109/TVLSI.2016.2589318},
timestamp = {Tue, 05 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HoLCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HosseiniSL17,
author = {S. Rasool Hosseini and
Mehdi Saberi and
Reza Lotfi},
title = {A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1154--1158},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2604377},
doi = {10.1109/TVLSI.2016.2604377},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HosseiniSL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HouZ17,
author = {Chen Hou and
Qianchuan Zhao},
title = {Stopping-Time Management of Smart Sensing Nodes Based on Tradeoffs
Between Accuracy and Power Consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2472--2485},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2712748},
doi = {10.1109/TVLSI.2017.2712748},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HouZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehCW17,
author = {Tong{-}Yu Hsieh and
Tsung{-}Liang Chih and
Mei{-}Jung Wu},
title = {Cost-Effective Enhancement on Both Yield and Reliability for Cache
Designs Based on Performance Degradation Tolerance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2434--2448},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2711924},
doi = {10.1109/TVLSI.2017.2711924},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehCW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuDHLCC17,
author = {Boyu Hu and
Yuan Du and
Rulin Huang and
Jeffrey Lee and
Young{-}Kai Chen and
Mau{-}Chung Frank Chang},
title = {An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode
{PAM-4} Wireline Transmitter Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3260--3264},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2737523},
doi = {10.1109/TVLSI.2017.2737523},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuDHLCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuSW17,
author = {Guanghui Hu and
Jin Sha and
Zhongfeng Wang},
title = {High-Speed Parallel {LFSR} Architectures Based on Improved State-Space
Transformations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1159--1163},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2608921},
doi = {10.1109/TVLSI.2016.2608921},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuSW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HudaA17,
author = {Safeen Huda and
Jason Helge Anderson},
title = {Leveraging Unused Resources for Energy Optimization of {FPGA} Interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2307--2320},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2691409},
doi = {10.1109/TVLSI.2017.2691409},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HudaA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HussainSCUMM17,
author = {Arshad Hussain and
Sai{-}Weng Sin and
Chi{-}Hang Chan and
Ben Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {Active-Passive {\(\Delta\)}{\(\Sigma\)} Modulator for High-Resolution
and Low-Power Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {364--374},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2580712},
doi = {10.1109/TVLSI.2016.2580712},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HussainSCUMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IeongLLMVM17,
author = {Chio{-}In Ieong and
Mingzhong Li and
Man{-}Kay Law and
Pui{-}In Mak and
Mang I Vai and
Rui Paulo Martins},
title = {A 0.45 {V} 147-375 nW {ECG} Compression Processor With Wavelet Shrinkage
and Adaptive Temporal Decimation Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1307--1319},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2638826},
doi = {10.1109/TVLSI.2016.2638826},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IeongLLMVM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IngemarssonKQG17,
author = {Carl Ingemarsson and
Petter Kallstrom and
Fahad Qureshi and
Oscar Gustafsson},
title = {Efficient {FPGA} Mapping of Pipeline {SDF} {FFT} Cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2486--2497},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2710479},
doi = {10.1109/TVLSI.2017.2710479},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/IngemarssonKQG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IslamG17,
author = {Riadul Islam and
Matthew R. Guthaus},
title = {{CMCS:} Current-Mode Clock Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1054--1062},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2605580},
doi = {10.1109/TVLSI.2016.2605580},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IslamG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainMS17,
author = {Palkesh Jain and
Vivek Mishra and
Sachin S. Sapatnekar},
title = {Fast Stochastic Analysis of Electromigration in Power Distribution
Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2512--2524},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2706520},
doi = {10.1109/TVLSI.2017.2706520},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JainMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JangCALK17,
author = {Jaewon Jang and
Minho Cheong and
Jin{-}Ho Ahn and
Sung Kyu Lim and
Sungho Kang},
title = {Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1178--1182},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2623810},
doi = {10.1109/TVLSI.2016.2623810},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JangCALK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JeyapaulFAS17,
author = {Reiley Jeyapaul and
Roberto Flores and
Alfonso {\'{A}}vila and
Aviral Shrivastava},
title = {Systematic Methodology for the Quantitative Analysis of Pipeline-Register
Reliability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {547--555},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2574642},
doi = {10.1109/TVLSI.2016.2574642},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JeyapaulFAS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JinKHMS17,
author = {Wei Jin and
Seongjong Kim and
Weifeng He and
Zhigang Mao and
Mingoo Seok},
title = {In Situ Error Detection Techniques in Ultralow Voltage Pipelines:
Analysis and Optimizations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1032--1043},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2625598},
doi = {10.1109/TVLSI.2016.2625598},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JinKHMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JingJCZJLL17,
author = {Naifeng Jing and
Shunning Jiang and
Shuang Chen and
Jingjie Zhang and
Li Jiang and
Chao Li and
Xiaoyao Liang},
title = {Bank Stealing for a Compact and Efficient Register File Architecture
in {GPGPU}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {520--533},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2584623},
doi = {10.1109/TVLSI.2016.2584623},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JingJCZJLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoshiS17,
author = {Archit Joshi and
Mukul Sarkar},
title = {Nonlinearity Estimation for Compensation of Phase Interpolator in
Bang-Bang CDRs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {388--392},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2574962},
doi = {10.1109/TVLSI.2016.2574962},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoshiS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JungSPL17,
author = {Moongon Jung and
Taigon Song and
Yarui Peng and
Sung Kyu Lim},
title = {Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2109--2117},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2670508},
doi = {10.1109/TVLSI.2017.2670508},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JungSPL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JuracyMKA17,
author = {Leonardo Rezende Juracy and
Matheus Trevisan Moreira and
Felipe Augusto Kuentzer and
Alexandre de Morais Amory},
title = {Optimized Design of an {LSSD} Scan Cell},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {765--768},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2589548},
doi = {10.1109/TVLSI.2016.2589548},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JuracyMKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KanduriHRLJTD17,
author = {Anil Kanduri and
Mohammad Hashem Haghbayan and
Amir M. Rahmani and
Pasi Liljeberg and
Axel Jantsch and
Hannu Tenhunen and
Nikil D. Dutt},
title = {Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2749--2762},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2694388},
doi = {10.1109/TVLSI.2017.2694388},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KanduriHRLJTD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KangCP17,
author = {Gyuseong Kang and
Woong Choi and
Jongsun Park},
title = {Embedded DRAM-Based Memory Customization for Low-Cost {FFT} Processor
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3484--3494},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2752265},
doi = {10.1109/TVLSI.2017.2752265},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KangCP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KapadiaP17,
author = {Nishit Ashok Kapadia and
Sudeep Pasricha},
title = {A Runtime Framework for Robust Application Scheduling With Adaptive
Parallelism in the Dark-Silicon Era},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {534--546},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2594238},
doi = {10.1109/TVLSI.2016.2594238},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KapadiaP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarimiRM17,
author = {Maryam Karimi and
Nezam Rohbani and
Seyed Ghassem Miremadi},
title = {A Low Area Overhead {NBTI/PBTI} Sensor for {SRAM} Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3138--3151},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2734839},
doi = {10.1109/TVLSI.2017.2734839},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarimiRM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KazimirskyTEF17,
author = {Amit Kazimirsky and
Adam Teman and
Noa Edri and
Alexander Fish},
title = {A 0.65-V, 500-MHz Integrated Dynamic and Static {RAM} for Error Tolerant
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2411--2418},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2712613},
doi = {10.1109/TVLSI.2017.2712613},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KazimirskyTEF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhalidPC17,
author = {Ayesha Khalid and
Goutam Paul and
Anupam Chattopadhyay},
title = {RC4-AccSuite: {A} Hardware Acceleration Suite for RC4-Like Stream
Ciphers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1072--1084},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2606554},
doi = {10.1109/TVLSI.2016.2606554},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhalidPC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanB17,
author = {Zia Uddin Ahamed Khan and
Mohammed Benaissa},
title = {High-Speed and Low-Latency {ECC} Processor Implementation Over GF(2\({}^{\mbox{m}}\))
on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {165--176},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2574620},
doi = {10.1109/TVLSI.2016.2574620},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanKK17,
author = {Muhammad Umar Karim Khan and
Asim Khan and
Chong{-}Min Kyung},
title = {EBSCam: Background Subtraction for Ubiquitous Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {35--47},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2567485},
doi = {10.1109/TVLSI.2016.2567485},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanKK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhoramiS17,
author = {Ata Khorami and
Mohammad Sharifkhani},
title = {An Efficient Fast Switching Procedure for Stepwise Capacitor Chargers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {705--713},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2599029},
doi = {10.1109/TVLSI.2016.2599029},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhoramiS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KiamehrEGT17,
author = {Saman Kiamehr and
Mojtaba Ebrahimi and
Mohammad Saber Golanbari and
Mehdi Baradaran Tahoori},
title = {Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency
of Near-Threshold Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2017--2026},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2669375},
doi = {10.1109/TVLSI.2017.2669375},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KiamehrEGT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimAAKCPYLHYL17,
author = {SangYun Kim and
Hamed Abbasizadeh and
Imran Ali and
HongJin Kim and
SungHun Cho and
YoungGun Pu and
Sang{-}Sun Yoo and
Minjae Lee and
Keum{-}Cheol Hwang and
Youngoo Yang and
Kang{-}Yoon Lee},
title = {An Inductive 2-D Position Detection {IC} With 99.8{\%} Accuracy for
Automotive {EMR} Gear Control System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1731--1741},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2651112},
doi = {10.1109/TVLSI.2017.2651112},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimAAKCPYLHYL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimCCDPMM17,
author = {Ryan Gary Kim and
Wonje Choi and
Zhuo Chen and
Janardhan Rao Doppa and
Partha Pratim Pande and
Diana Marculescu and
Radu Marculescu},
title = {Imitation Learning for Dynamic {VFI} Control in Large-Scale Manycore
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2458--2471},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2700726},
doi = {10.1109/TVLSI.2017.2700726},
timestamp = {Fri, 12 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimCCDPMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKL17,
author = {Hyeonggyu Kim and
Soontae Kim and
Jooheung Lee},
title = {Write-Amount-Aware Management Policies for {STT-RAM} Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1588--1592},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2620168},
doi = {10.1109/TVLSI.2016.2620168},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimLCK17,
author = {Jooyoung Kim and
Woosung Lee and
Keewon Cho and
Sungho Kang},
title = {Hardware-Efficient Built-In Redundancy Analysis for Memory With Various
Spares},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {844--856},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2606499},
doi = {10.1109/TVLSI.2016.2606499},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimLCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimM17,
author = {Dae{-}Hyun Kim and
Linda Milor},
title = {An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2045--2058},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2671790},
doi = {10.1109/TVLSI.2017.2671790},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSCWT17,
author = {Taeyoung Kim and
Zeyu Sun and
Hai{-}Bao Chen and
Hai Wang and
Sheldon X.{-}D. Tan},
title = {Energy and Lifetime Optimizations for Dark Silicon Manycore Microprocessor
Considering Both Hard and Soft Errors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2561--2574},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2707401},
doi = {10.1109/TVLSI.2017.2707401},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSCWT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSH17,
author = {Sihwan Kim and
Sahil Shah and
Jennifer Hasler},
title = {Calibration of Floating-Gate SoC {FPAA} System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2649--2657},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2710020},
doi = {10.1109/TVLSI.2017.2710020},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimWF17,
author = {HoonSeok Kim and
Chanyoun Won and
Paul D. Franzon},
title = {Corrections to "Crosstalk-Canceling Multimode Interconnect Using Transmitter
Encoding"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1792},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2647621},
doi = {10.1109/TVLSI.2016.2647621},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimWF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KongSL17,
author = {Derui Kong and
Dongwon Seo and
Sang Min Lee},
title = {Analysis and Reduction of Nonidealities in Stacked-Transistor Current
Sources},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {774--778},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2597182},
doi = {10.1109/TVLSI.2016.2597182},
timestamp = {Tue, 29 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KongSL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KozumaONAKIIYMI17,
author = {Munehiro Kozuma and
Yuki Okamoto and
Takashi Nakagawa and
Takeshi Aoki and
Yoshiyuki Kurokawa and
Takayuki Ikeda and
Yoshinori Ieda and
Naoto Yamade and
Hidekazu Miyairi and
Makoto Ikeda and
Masahiro Fujita and
Shunpei Yamazaki},
title = {Subthreshold Operation of {CAAC-IGZO} {FPGA} by Overdriving of Programmable
Routing Switch and Programmable Power Switch},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {125--138},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2571744},
doi = {10.1109/TVLSI.2016.2571744},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KozumaONAKIIYMI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KraakTAHWCC17,
author = {Daniel Kraak and
Mottaqiallah Taouil and
Innocent Agbo and
Said Hamdioui and
Pieter Weckx and
Stefan Cosemans and
Francky Catthoor},
title = {Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic
Workloads},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3464--3472},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2746798},
doi = {10.1109/TVLSI.2017.2746798},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KraakTAHWCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarC17,
author = {Sachin Kumar and
Chip{-}Hong Chang},
title = {A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli
Set {RNS} 2\({}^{\mbox{n}}\)-1, 2\({}^{\mbox{n}}\), 2\({}^{\mbox{n}}\)+
1, 2\({}^{\mbox{n+1}}\)-1, 2\({}^{\mbox{n-1}}\)-1},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3521--3533},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2748984},
doi = {10.1109/TVLSI.2017.2748984},
timestamp = {Fri, 04 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarZL17,
author = {Sumeet S. Kumar and
Amir Zjajo and
Ren{\'{e}} van Leuken},
title = {Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D
Stacked Multiprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1549--1562},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2642587},
doi = {10.1109/TVLSI.2016.2642587},
timestamp = {Tue, 13 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarZL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KwonBCK17,
author = {Soon{-}Chan Kwon and
Jong{-}Min Baek and
Jong{-}Moon Choi and
Kee{-}Won Kwon},
title = {A Fast and Reliable Cross-Point Three-State/Cell ReRAM},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1622--1631},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2645384},
doi = {10.1109/TVLSI.2016.2645384},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KwonBCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LaiH17,
author = {Bo{-}Cheng Charles Lai and
Kun{-}Hua Huang},
title = {An Efficient Hierarchical Banking Structure for Algorithmic Multiported
Memory on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2776--2788},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2717448},
doi = {10.1109/TVLSI.2017.2717448},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LaiH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LaiL17,
author = {Bo{-}Cheng Charles Lai and
Jiun{-}Liang Lin},
title = {Efficient Designs of Multiported Memory on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {139--150},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2568579},
doi = {10.1109/TVLSI.2016.2568579},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LaiL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LecomteFM17,
author = {Maxime Lecomte and
Jacques Fournier and
Philippe Maurine},
title = {An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit
Identification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3317--3330},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2627525},
doi = {10.1109/TVLSI.2016.2627525},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LecomteFM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeCAC17,
author = {Jinho Lee and
Jongwook Chung and
Jung Ho Ahn and
Kiyoung Choi},
title = {Excavating the Hidden Parallelism Inside {DRAM} Architectures With
Buffered Compares},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1793--1806},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2655722},
doi = {10.1109/TVLSI.2017.2655722},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeCAC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKK17,
author = {Taeho Lee and
Yong{-}Hun Kim and
Lee{-}Sup Kim},
title = {A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced {DCO}
Supply Noise Sensitivity Utilizing Coupling Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {380--384},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2566927},
doi = {10.1109/TVLSI.2016.2566927},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKKS17,
author = {Sang Min Lee and
Namsoo Kim and
Derui Kong and
Dongwon Seo},
title = {A {DAC} With an Impedance Attenuator and Distortion Analysis Using
Volterra Series},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2929--2938},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2723485},
doi = {10.1109/TVLSI.2017.2723485},
timestamp = {Tue, 29 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLLJ17,
author = {Pil{-}Ho Lee and
Han{-}Yeol Lee and
Hyun Bae Lee and
Young{-}Chan Jang},
title = {An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s
Chip-to-Chip Interfaces With Source-Synchronous Clock},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1386--1396},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2639289},
doi = {10.1109/TVLSI.2016.2639289},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLLJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLWEGAW17,
author = {Hochul Lee and
Albert Lee and
Shaodi Wang and
Farbod Ebrahimi and
Puneet Gupta and
Pedram Khalili Amiri and
Kang L. Wang},
title = {A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random
Access Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2027--2034},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2670502},
doi = {10.1109/TVLSI.2017.2670502},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLWEGAW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeMFY17,
author = {Chiou{-}Yng Lee and
Pramod Kumar Meher and
Chia{-}Chen Fan and
Shyan{-}Ming Yuan},
title = {Low-Complexity Digit-Serial Multiplier Over {\textdollar}GF(2\{m\}){\textdollar}
Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {735--746},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2605183},
doi = {10.1109/TVLSI.2016.2605183},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeMFY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeePC17,
author = {Yu{-}Min Lee and
Kuan{-}Te Pan and
Chun Chen},
title = {NaPer: {A} {TSV} Noise-Aware Placer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1703--1713},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2645230},
doi = {10.1109/TVLSI.2016.2645230},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeePC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeSKY17,
author = {Jinsu Lee and
Dongjoo Shin and
Youchang Kim and
Hoi{-}Jun Yoo},
title = {A 17.5-fJ/bit Energy-Efficient Analog {SRAM} for Mixed-Signal Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2714--2723},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2664069},
doi = {10.1109/TVLSI.2017.2664069},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeSKY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeTLCW17,
author = {Tzung{-}Je Lee and
Tsung{-}Yi Tsai and
Wei Lin and
U{-}Fat Chio and
Chua{-}Chin Wang},
title = {A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm {CMOS}
Mixed-Voltage Output Buffer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3166--3174},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2736782},
doi = {10.1109/TVLSI.2017.2736782},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeTLCW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeTZBW17,
author = {Sae Kyu Lee and
Tao Tong and
Xuan Zhang and
David M. Brooks and
Gu{-}Yeon Wei},
title = {A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated
Switched-Capacitor {DC-DC} Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1271--1284},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2633805},
doi = {10.1109/TVLSI.2016.2633805},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeTZBW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeviFK17,
author = {Itamar Levi and
Alexander Fish and
Osnat Keren},
title = {{CPA} Secured Data-Dependent Delay-Assignment Methodology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {608--620},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2592967},
doi = {10.1109/TVLSI.2016.2592967},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeviFK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCHCW17,
author = {Huai{-}Ting Li and
Ching{-}Yao Chou and
Yuan{-}Ting Hsieh and
Wei{-}Ching Chu and
An{-}Yeu Wu},
title = {Variation-Aware Reliable Many-Core System Design by Exploiting Inherent
Core Redundancy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2803--2816},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2715803},
doi = {10.1109/TVLSI.2017.2715803},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCHCW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiHWCWDN17,
author = {Yun{-}Jui Li and
Ching{-}Yi Huang and
Chia{-}Cheng Wu and
Yung{-}Chih Chen and
Chun{-}Yao Wang and
Suman Datta and
Vijaykrishnan Narayanan},
title = {Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor
Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1477--1489},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2639533},
doi = {10.1109/TVLSI.2016.2639533},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiHWCWDN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiJKM17,
author = {Dawei Li and
Siddhartha Joshi and
Ji{-}Hoon Kim and
Seda Ogrenci Memik},
title = {End-to-End Analysis of Integration for Thermocouple-Based Sensors
Into 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2498--2511},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2699040},
doi = {10.1109/TVLSI.2017.2699040},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiJKM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiJL17,
author = {Shunbin Li and
Yingtao Jiang and
Peng Liu},
title = {An Adaptive {PAM-4} Analog Equalizer With Boosting-State Detection
in the Time Domain},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2907--2916},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2720750},
doi = {10.1109/TVLSI.2017.2720750},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiJL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiKKC17,
author = {Chun{-}Hsing Li and
Chun{-}Lin Ko and
Ming{-}Ching Kuo and
Da{-}Chiang Chang},
title = {A 7.1-mW K/K\({}_{\mbox{a}}\)-Band Mixer With Configurable Bondwire
Resonators in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2635--2648},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2703807},
doi = {10.1109/TVLSI.2017.2703807},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiKKC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiYMLY17,
author = {Xiangyu Li and
Chaoqun Yang and
Jiangsha Ma and
Yongchang Liu and
Shujuan Yin},
title = {Energy-Efficient Side-Channel Attack Countermeasure With Awareness
and Hybrid Configuration Based on It},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3355--3368},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2752212},
doi = {10.1109/TVLSI.2017.2752212},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiYMLY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZ17,
author = {Yongyuan Li and
Zhangming Zhu},
title = {A 30-W 90{\%} Efficiency Dual-Mode Controlled {DC-DC} Controller With
Power Over Ethernet Interface for Power Device},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1943--1953},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2662662},
doi = {10.1109/TVLSI.2017.2662662},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZCMXY17,
author = {Zhan{-}Hui Li and
Tao{-}Tao Zhu and
Zhi{-}Jian Chen and
Jian{-}Yi Meng and
Xiaoyan Xiang and
Xiaolang Yan},
title = {Eliminating Timing Errors Through Collaborative Design to Maximize
the Throughput},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {670--682},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2587810},
doi = {10.1109/TVLSI.2016.2587810},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZCMXY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LimLLSKLC17,
author = {Younghyun Lim and
Jeonghyun Lee and
Yongsun Lee and
Seong{-}Sik Song and
Hong{-}Teuk Kim and
Ockgoo Lee and
Jaehyouk Choi},
title = {An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain
Stabilizing Technique for High Power-Supply Rejection Over a Wide
Range of Load Current},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3006--3018},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2742603},
doi = {10.1109/TVLSI.2017.2742603},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LimLLSKLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LimMBK17,
author = {ChaiYong Lim and
Debashis Mandal and
Bertan Bakkaloglu and
Sayfe Kiaei},
title = {A 50-mA 99.2{\%} Peak Current Efficiency, 250-ns Settling Time Digital
Low-Dropout Regulator With Transient Enhanced {PI} Controller},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2360--2370},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2682862},
doi = {10.1109/TVLSI.2017.2682862},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LimMBK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinC17,
author = {Ching{-}Wen Lin and
Chung{-}Ho Chen},
title = {A Processor and Cache Online Self-Testing Methodology for OS-Managed
Platform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2346--2359},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2698506},
doi = {10.1109/TVLSI.2017.2698506},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCLCCZ17,
author = {Hesheng Lin and
Wing Chun Chan and
Wai Kwong Lee and
Zhirong Chen and
Mansun Chan and
Min Zhang},
title = {High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift
Enhancement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2164--2173},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2676822},
doi = {10.1109/TVLSI.2017.2676822},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCLCCZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinSHWT17,
author = {Jin{-}Fa Lin and
Ming{-}Hwa Sheu and
Yin{-}Tsung Hwang and
Chen{-}Syuan Wong and
Ming{-}Yan Tsai},
title = {Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design
Based on Logic Structure Reduction Schemes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3033--3044},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2729884},
doi = {10.1109/TVLSI.2017.2729884},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinSHWT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinYW17,
author = {Jun Lin and
Zhiyuan Yan and
Zhongfeng Wang},
title = {Efficient Soft Cancelation Decoder Architectures for Polar Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {87--99},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2577883},
doi = {10.1109/TVLSI.2016.2577883},
timestamp = {Sat, 20 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuJNM17,
author = {Yu Liu and
Yier Jin and
Aria Nosratinia and
Yiorgos Makris},
title = {Silicon Demonstration of Hardware Trojan Design and Detection in Wireless
Cryptographic ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1506--1519},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2633348},
doi = {10.1109/TVLSI.2016.2633348},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuJNM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLO17,
author = {Yangxurui Liu and
Liang Liu and
Viktor {\"{O}}wall},
title = {Architecture Design of a Memory Subsystem for Massive {MIMO} Baseband
Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2976--2980},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2732062},
doi = {10.1109/TVLSI.2017.2732062},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuSC17,
author = {Qing Liu and
Wei Shu and
Joseph S. Chang},
title = {A 400-MS/s 10-b 2-b/Step {SAR} {ADC} With 52-dB {SNDR} and 5.61-mW
Power Dissipation in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3444--3454},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2747132},
doi = {10.1109/TVLSI.2017.2747132},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuTXYZ17,
author = {Cang Liu and
Chuan Tang and
Zuocheng Xing and
Luechao Yuan and
Yang Zhang},
title = {Hardware Architecture Based on Parallel Tiled {QRD} Algorithm for
Future {MIMO} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1714--1724},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2645841},
doi = {10.1109/TVLSI.2016.2645841},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuTXYZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuYWD17,
author = {Xue Liu and
Xin{-}Xin Yan and
Ze{-}ke Wang and
Qingxu Deng},
title = {Design and {FPGA} Implementation of a Reconfigurable Digital Down
Converter for Wideband Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3548--3552},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2748603},
doi = {10.1109/TVLSI.2017.2748603},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuYWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuHYL17,
author = {Weina Lu and
Yu Hu and
Jing Ye and
Xiaowei Li},
title = {Going Cooler With Timing-Constrained TeSHoP: {A} Temperature Sensing-Based
Hotspot-Driven Placement Technique for FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2525--2537},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2707120},
doi = {10.1109/TVLSI.2017.2707120},
timestamp = {Mon, 22 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuHYL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuY17,
author = {Zhonghai Lu and
Yuan Yao},
title = {Dynamic Traffic Regulation in NoC-Based Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {556--569},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2584781},
doi = {10.1109/TVLSI.2016.2584781},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoZWHL17,
author = {Haowen Luo and
Wei Zhang and
Yang Wang and
Yan Hu and
Yanyan Liu},
title = {An Algorithm for Improving the Throughput of Serial Low-Complexity
Chase Soft-Decision Reed-Solomon Decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3539--3542},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2746139},
doi = {10.1109/TVLSI.2017.2746139},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoZWHL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaCDH17,
author = {Yue Ma and
Thidapat Chantem and
Robert P. Dick and
Xiaobo Sharon Hu},
title = {Improving System-Level Lifetime Reliability of Multicore Soft Real-Time
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1895--1905},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2669144},
doi = {10.1109/TVLSI.2017.2669144},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaCDH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaganaSMD17,
author = {Jonathon Maga{\~{n}}a and
Daohang Shi and
Jackson Melchert and
Azadeh Davoodi},
title = {Are Proximity Attacks a Threat to the Security of Split Manufacturing
of Integrated Circuits?},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3406--3419},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2748018},
doi = {10.1109/TVLSI.2017.2748018},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaganaSMD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahendraMD17,
author = {Telajala Venkata Mahendra and
Sandeep Mishra and
Anup Dandapat},
title = {Self-Controlled High-Performance Precharge-Free Content-Addressable
Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2388--2392},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2685427},
doi = {10.1109/TVLSI.2017.2685427},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MahendraMD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahzoonA17,
author = {Alireza Mahzoon and
Bijan Alizadeh},
title = {OptiFEX: {A} Framework for Exploring Area-Efficient Floating Point
Expressions on FPGAs With Optimized Exponent/Mantissa Widths},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {198--209},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2570252},
doi = {10.1109/TVLSI.2016.2570252},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahzoonA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MannMRSKXGVPW17,
author = {Randy W. Mann and
William McMahon and
Yoann Mamy Randriamihaja and
Yuncheng Song and
Ajay Anand Kallianpur and
Sheng Xie and
Akhilesh Gautam and
Joseph Versaggi and
Biju Parameshwaran and
Chad E. Weintraub},
title = {Bias-Induced Healing of {\textdollar}V{\_}\{{\textbackslash}text \{min\}\}{\textdollar}
Failures in Advanced {SRAM} Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {660--669},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2598160},
doi = {10.1109/TVLSI.2016.2598160},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MannMRSKXGVPW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MannPXMVFGTZZW17,
author = {Randy W. Mann and
Sandeep Puri and
Sheng Xie and
Daniel Marienfeld and
Joseph Versaggi and
Bianzhu Fu and
Michael Gribelyuk and
Ratheesh R. Thankalekshmi and
Xiaoqiang Zhang and
Hui Zang and
Chad E. Weintraub},
title = {Array Termination Impacts in Advanced {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2449--2457},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2713124},
doi = {10.1109/TVLSI.2017.2713124},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MannPXMVFGTZZW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaoCYC17,
author = {Manqing Mao and
Pai{-}Yu Chen and
Shimeng Yu and
Chaitali Chakrabarti},
title = {A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM
Cross-Point Array System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1611--1621},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2651647},
doi = {10.1109/TVLSI.2017.2651647},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaoCYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaroofK17,
author = {Naeem Maroof and
Bai{-}Sun Kong},
title = {10T {SRAM} Using Half-V\({}_{\mbox{DD}}\) Precharge and Row-Wise Dynamically
Powered Read Port for Low Switching Power and Ultralow {RBL} Leakage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1193--1203},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2637918},
doi = {10.1109/TVLSI.2016.2637918},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaroofK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MatsuiAST17,
author = {Chihiro Matsui and
Asuka Arakawa and
Chao Sun and
Ken Takeuchi},
title = {Write Order-Based Garbage Collection Scheme for an {LBA} Scrambler
Integrated {SSD}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {510--519},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2594200},
doi = {10.1109/TVLSI.2016.2594200},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MatsuiAST17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MeriboutT17,
author = {Mahmoud M{\'{e}}ribout and
Samir Teniou},
title = {A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical
Capacitance Tomography Imaging Using Interframe Correlation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1320--1328},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2636184},
doi = {10.1109/TVLSI.2016.2636184},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MeriboutT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MohantySASC17,
author = {Abinash Mohanty and
Ketul B. Sutaria and
Hiromitsu Awano and
Takashi Sato and
Yu Cao},
title = {{RTN} in Scaled Transistors for On-Chip Random Seed Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2248--2257},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2687762},
doi = {10.1109/TVLSI.2017.2687762},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MohantySASC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MohsinS17,
author = {K. M. Mohsin and
Ashok Srivastava},
title = {Modeling of Joule Heating Induced Effects in Multiwall Carbon Nanotube
Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3089--3098},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2737884},
doi = {10.1109/TVLSI.2017.2737884},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MohsinS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MondalCK17,
author = {Saikat Mondal and
Sang{-}Bock Cho and
Bruce C. Kim},
title = {Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground
{TSV} Shielding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {308--318},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2568755},
doi = {10.1109/TVLSI.2016.2568755},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MondalCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Montazerolghaem17,
author = {Mohammad Ali Montazerolghaem and
Tohid Moosazadeh and
Mohammad Yavari},
title = {A Single Channel Split {ADC} Structure for Digital Background Calibration
in Pipelined ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1563--1567},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2641259},
doi = {10.1109/TVLSI.2016.2641259},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Montazerolghaem17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MopuriA17,
author = {Suresh Mopuri and
Amit Acharyya},
title = {Low-Complexity Methodology for Complex Square-Root Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3255--3259},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2740343},
doi = {10.1109/TVLSI.2017.2740343},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MopuriA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Mora-GutierrezJ17,
author = {Jos{\'{e}} Miguel Mora{-}Gutierrez and
Carlos Jes{\'{u}}s Jim{\'{e}}nez{-}Fern{\'{a}}ndez and
Manuel Valencia{-}Barrero},
title = {Multiradix Trivium Implementations for Low-Power IoT Hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3401--3405},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2736063},
doi = {10.1109/TVLSI.2017.2736063},
timestamp = {Sun, 23 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Mora-GutierrezJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MrugalskiRSTW17,
author = {Grzegorz Mrugalski and
Janusz Rajski and
Jedrzej Solecki and
Jerzy Tyszer and
Chen Wang},
title = {Trimodal Scan-Based Test Paradigm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1112--1125},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2608984},
doi = {10.1109/TVLSI.2016.2608984},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MrugalskiRSTW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MulaGD17,
author = {Subrahmanyam Mula and
Vinay Chakravarthi Gogineni and
Anindya Sundar Dhar},
title = {Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2588--2601},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2702171},
doi = {10.1109/TVLSI.2017.2702171},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MulaGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NajafiJLRBH17,
author = {M. Hassan Najafi and
Shiva Jamali{-}Zavareh and
David J. Lilja and
Marc D. Riedel and
Kia Bazargan and
Ramesh Harjani},
title = {Time-Encoded Values for Highly Efficient Stochastic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1644--1657},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2645902},
doi = {10.1109/TVLSI.2016.2645902},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NajafiJLRBH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NaminMA17,
author = {Parham Hosseinzadeh Namin and
Roberto Muscedere and
Majid Ahmadi},
title = {Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation
for a Class of Finite Fields},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1632--1643},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2646479},
doi = {10.1109/TVLSI.2016.2646479},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NaminMA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NaminWA17,
author = {Shoaleh Hashemi Namin and
Huapeng Wu and
Majid Ahmadi},
title = {Low-Power Design for a Digit-Serial Polynomial Basis Finite Field
Multiplier Using Factoring Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {441--449},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2585980},
doi = {10.1109/TVLSI.2016.2585980},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NaminWA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NarayanaswamyKS17,
author = {Swaminathan Narayanaswamy and
Matthias Kauer and
Sebastian Steinhorst and
Martin Lukasiewycz and
Samarjit Chakraborty},
title = {Modular Active Charge Balancing for Scalable Battery Packs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {974--987},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2611526},
doi = {10.1109/TVLSI.2016.2611526},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NarayanaswamyKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NevesTR17,
author = {Nuno Neves and
Pedro Tom{\'{a}}s and
Nuno Roma},
title = {Adaptive In-Cache Streaming for Efficient Data Management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2130--2143},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2671405},
doi = {10.1109/TVLSI.2017.2671405},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NevesTR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NguyenXTNHB17,
author = {Hoang Anh Du Nguyen and
Lei Xie and
Mottaqiallah Taouil and
Razvan Nane and
Said Hamdioui and
Koen Bertels},
title = {On the Implementation of Computation-in-Memory Parallel Adder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2206--2219},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2690571},
doi = {10.1109/TVLSI.2017.2690571},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NguyenXTNHB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NicholsonIJHL17,
author = {Andrew P. Nicholson and
Astria Nur Irfansyah and
Julian Jenkins and
Tara Julia Hamilton and
Torsten Lehmann},
title = {A Statistical Design Approach Using Fixed and Variable Width Transconductors
for Positive-Feedback Gain-Enhancement OTAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1966--1977},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2657885},
doi = {10.1109/TVLSI.2017.2657885},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NicholsonIJHL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OhJKPYJ17,
author = {Tae Woo Oh and
Hanwool Jeong and
Kyoman Kang and
Juhyun Park and
Younghwi Yang and
Seong{-}Ook Jung},
title = {Power-Gated 9T {SRAM} Cell for Low-Energy Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1183--1187},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2623601},
doi = {10.1109/TVLSI.2016.2623601},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OhJKPYJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OkuharaFUA17,
author = {Hayate Okuhara and
Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {Power Optimization Methodology for Ultralow Power Microcontroller
With Silicon on Thin {BOX} {MOSFET}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1578--1582},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2635675},
doi = {10.1109/TVLSI.2016.2635675},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OkuharaFUA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OmanaRFMTG17,
author = {Martin Oma{\~{n}}a and
Daniele Rossi and
Filippo Fuzzi and
Cecilia Metra and
Chandra Tirumurti and
Rajesh Galivanche},
title = {Scalable Approach for Power Droop Reduction During Scan-Based Logic
{BIST}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {238--246},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2572606},
doi = {10.1109/TVLSI.2016.2572606},
timestamp = {Sun, 20 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OmanaRFMTG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OnizawaKSAKH17,
author = {Naoya Onizawa and
Shunsuke Koshita and
Shuichi Sakamoto and
Masahide Abe and
Masayuki Kawamata and
Takahiro Hanyu},
title = {Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2724--2735},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2687404},
doi = {10.1109/TVLSI.2017.2687404},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OnizawaKSAKH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Ortin-ObonTRYB17,
author = {Marta Ort{\'{\i}}n{-}Ob{\'{o}}n and
Mahdi Tala and
Luca Ramini and
V{\'{\i}}ctor Vi{\~{n}}als Y{\'{u}}fera and
Davide Bertozzi},
title = {Contrasting Laser Power Requirements of Wavelength-Routed Optical
NoC Topologies Subject to the Floorplanning, Placement, and Routing
Constraints of a 3-D-Stacked System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2081--2094},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2677779},
doi = {10.1109/TVLSI.2017.2677779},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Ortin-ObonTRYB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PandaVSRR17,
author = {Priyadarshini Panda and
Swagath Venkataramani and
Abhronil Sengupta and
Anand Raghunathan and
Kaushik Roy},
title = {Energy-Efficient Object Detection Using Semantic Decomposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2673--2677},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2707077},
doi = {10.1109/TVLSI.2017.2707077},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PandaVSRR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkBKS17,
author = {Sung Joo Park and
Bumhee Bae and
Joungho Kim and
Madhavan Swaminathan},
title = {Application of Machine Learning for Optimization of 3-D Integrated
Circuits and Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1856--1865},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2656843},
doi = {10.1109/TVLSI.2017.2656843},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkBKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkLK17,
author = {Jungwoo Park and
Jongmin Lee and
Soontae Kim},
title = {A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture
for Low-Energy Consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {793--805},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2603164},
doi = {10.1109/TVLSI.2016.2603164},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkLK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkSK17,
author = {Ji{-}Hoon Park and
Hyun{-}Seung Seo and
Bai{-}Sun Kong},
title = {Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {779--782},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2595627},
doi = {10.1109/TVLSI.2016.2595627},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkSK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PathakGPB17,
author = {Shalini Pathak and
Anuj Grover and
Mausumi Pohit and
Nitin Bansal},
title = {LoCCo-Based Scan Chain Stitching for Low-Power {DFT}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3227--3236},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2735864},
doi = {10.1109/TVLSI.2017.2735864},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PathakGPB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PathakHS17,
author = {Divya Pathak and
Houman Homayoun and
Ioannis Savidis},
title = {Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2538--2551},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2699644},
doi = {10.1109/TVLSI.2017.2699644},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PathakHS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaulinoFC17,
author = {Nuno Miguel Cardanha Paulino and
Jo{\~{a}}o Canas Ferreira and
Jo{\~{a}}o M. P. Cardoso},
title = {Generation of Customized Accelerators for Loop Pipelining of Binary
Instruction Traces},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {21--34},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2573640},
doi = {10.1109/TVLSI.2016.2573640},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PaulinoFC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamL17,
author = {Huyen Thi Pham and
Hanho Lee},
title = {Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary
{LDPC} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1787--1791},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2647985},
doi = {10.1109/TVLSI.2017.2647985},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PimentelBB17,
author = {Jon J. Pimentel and
Brent Bohnenstiehl and
Bevan M. Baas},
title = {Hybrid Hardware/Software Floating-Point Implementations for Optimized
Area and Throughput Tradeoffs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {100--113},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2580142},
doi = {10.1109/TVLSI.2016.2580142},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PimentelBB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz17,
author = {Irith Pomeranz},
title = {Selecting Replacements for Undetectable Path Delay Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1988--1992},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2670147},
doi = {10.1109/TVLSI.2017.2670147},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Potestad-Ordonez17,
author = {Francisco Eugenio Potestad{-}Ord{\'{o}}{\~{n}}ez and
Carlos Jes{\'{u}}s Jim{\'{e}}nez{-}Fern{\'{a}}ndez and
Manuel Valencia{-}Barrero},
title = {Vulnerability Analysis of Trivium {FPGA} Implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3380--3389},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2751151},
doi = {10.1109/TVLSI.2017.2751151},
timestamp = {Thu, 31 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Potestad-Ordonez17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PradhanB17,
author = {Manjari Pradhan and
Bhargab B. Bhattacharya},
title = {{COMEDI:} Combinatorial Election of Diagnostic Vectors From Detection
Test Sets for Logic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1467--1476},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2642343},
doi = {10.1109/TVLSI.2016.2642343},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PradhanB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QianBKPB17,
author = {Wenchao Qian and
Christopher Babecki and
Robert Karam and
Somnath Paul and
Swarup Bhunia},
title = {{ENFIRE:} {A} Spatio-Temporal Fine-Grained Reconfigurable Hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {177--188},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2578933},
doi = {10.1109/TVLSI.2016.2578933},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QianBKPB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RabozziDMLS17,
author = {Marco Rabozzi and
Gianluca Carlo Durelli and
Antonio Miele and
John Lillis and
Marco Domenico Santambrogio},
title = {Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible
Placements Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {151--164},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2562361},
doi = {10.1109/TVLSI.2016.2562361},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RabozziDMLS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahaVRR17,
author = {Arnab Raha and
Swagath Venkataramani and
Vijay Raghunathan and
Anand Raghunathan},
title = {Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {462--475},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2586379},
doi = {10.1109/TVLSI.2016.2586379},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RahaVRR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahmanSXFT17,
author = {Fahim Rahman and
Bicky Shakya and
Xiaolin Xu and
Domenic Forte and
Mark M. Tehranipoor},
title = {Security Beyond {CMOS:} Fundamentals, Applications, and Roadmap},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3420--3433},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2742943},
doi = {10.1109/TVLSI.2017.2742943},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RahmanSXFT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahmaniHMLJT17,
author = {Amir M. Rahmani and
Mohammad Hashem Haghbayan and
Antonio Miele and
Pasi Liljeberg and
Axel Jantsch and
Hannu Tenhunen},
title = {Reliability-Aware Runtime Power Management for Many-Core Systems in
the Dark Silicon Era},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {427--440},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2591798},
doi = {10.1109/TVLSI.2016.2591798},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RahmaniHMLJT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahmaniRM17,
author = {Kamran Rahmani and
Sandip Ray and
Prabhat Mishra},
title = {Postsilicon Trace Signal Selection Using Machine Learning Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {570--580},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2593902},
doi = {10.1109/TVLSI.2016.2593902},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RahmaniRM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RajaKZB17,
author = {Immanuel Raja and
Vishal Khatri and
Zaira Zahir and
Gaurab Banerjee},
title = {A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock
Generation Circuits in 130-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1044--1053},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2614695},
doi = {10.1109/TVLSI.2016.2614695},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RajaKZB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RajiG17,
author = {Mohsen Raji and
Behnam Ghavami},
title = {Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing
in the Presence of Process Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {247--260},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2569562},
doi = {10.1109/TVLSI.2016.2569562},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RajiG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RamezaniSC17,
author = {Reza Ramezani and
Yasser Sedaghat and
Juan Antonio Clemente},
title = {Reliability Improvement of Hardware Task Graphs via Configuration
Early Fetch},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1408--1420},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2631724},
doi = {10.1109/TVLSI.2016.2631724},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RamezaniSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RangachariBC17,
author = {Sundarrajan Rangachari and
Jaiganesh Balakrishnan and
Nitin Chandrachoodan},
title = {Scenario-Aware Dynamic Power Reduction Using Bias Addition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {450--461},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2601030},
doi = {10.1109/TVLSI.2016.2601030},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RangachariBC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReddyAK17,
author = {Raviteja P. Reddy and
Amit Acharyya and
S. Saqib Khursheed},
title = {A Cost-Effective Fault Tolerance Technique for Functional {TSV} in
3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2071--2080},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2681703},
doi = {10.1109/TVLSI.2017.2681703},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReddyAK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RefanAN17,
author = {Fatemeh Refan and
Bijan Alizadeh and
Zainalabedin Navabi},
title = {Bridging Presilicon and Postsilicon Debugging by Instruction-Based
Trace Signal Selection in Modern Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2059--2070},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2675380},
doi = {10.1109/TVLSI.2017.2675380},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RefanAN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RehmanS17,
author = {Sami Ur Rehman and
Ayman Shabra},
title = {A Temperature Estimation Method Using the Ratio of Emitter-to-Base
Voltages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2174--2182},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2681941},
doi = {10.1109/TVLSI.2017.2681941},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RehmanS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Renteria-MejiaV17,
author = {Claudia Patricia Renteria{-}Mejia and
Jaime Velasco{-}Medina},
title = {High-Throughput Ring-LWE Cryptoprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2332--2345},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2697841},
doi = {10.1109/TVLSI.2017.2697841},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Renteria-MejiaV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RohbaniEMT17,
author = {Nezam Rohbani and
Mojtaba Ebrahimi and
Seyed Ghassem Miremadi and
Mehdi Baradaran Tahoori},
title = {Bias Temperature Instability Mitigation via Adaptive Cache Size Management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1012--1022},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2606579},
doi = {10.1109/TVLSI.2016.2606579},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RohbaniEMT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RyuSPCB17,
author = {Hyuk Ryu and
Eun{-}Taek Sung and
Sangyong Park and
Je{-}Kwang Cho and
Donghyun Baek},
title = {Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search
Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1490--1496},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2627578},
doi = {10.1109/TVLSI.2016.2627578},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RyuSPCB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SadiCCWT17,
author = {Mehdi Sadi and
Gustavo K. Contreras and
Jifeng Chen and
LeRoy Winemberg and
Mark M. Tehranipoor},
title = {Design of Reliable SoCs With {BIST} Hardware and Machine Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3237--3250},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2734685},
doi = {10.1109/TVLSI.2017.2734685},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SadiCCWT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SanaullahC17,
author = {Muhammad Sanaullah and
Masud H. Chowdhury},
title = {Analytical Models of High-Speed {RLC} Interconnect Delay for Complex
and Real Poles},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1831--1841},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2654921},
doi = {10.1109/TVLSI.2017.2654921},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SanaullahC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarkarBDR17,
author = {Sumantra Sarkar and
Ayan Biswas and
Anindya Sundar Dhar and
Rahul M. Rao},
title = {Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With
Dynamically Varying Switching Characteristics},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3057--3066},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2730283},
doi = {10.1109/TVLSI.2017.2730283},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SarkarBDR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarmaRS17,
author = {Vineeth Sarma and
Chithira Ravi and
Bibhudatta Sahoo},
title = {Achieving Theoretical Limit of {SFDR} in Pipelined ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3175--3185},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2731262},
doi = {10.1109/TVLSI.2017.2731262},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SarmaRS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarsonSL17,
author = {Peter G. Sarson and
Gregor Schatzberger and
Friedrich Peter Leisenberger},
title = {Fast Bit Screening of Automotive Grade EEPROMs - Continuous Improvement
Exercise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1250--1260},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2634589},
doi = {10.1109/TVLSI.2016.2634589},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SarsonSL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchlachterCPE17,
author = {Jeremy Schlachter and
Vincent Camus and
Krishna V. Palem and
Christian C. Enz},
title = {Design and Applications of Approximate Circuits by Gate-Level Pruning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1694--1702},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2657799},
doi = {10.1109/TVLSI.2017.2657799},
timestamp = {Fri, 23 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SchlachterCPE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ScottiBTP17,
author = {Giuseppe Scotti and
Davide Bellizia and
Alessandro Trifiletti and
Gaetano Palumbo},
title = {Design of Low-Voltage High-Speed {CML} D-Latches in Nanometer {CMOS}
Technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3509--3520},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2750207},
doi = {10.1109/TVLSI.2017.2750207},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ScottiBTP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SenguptaK17,
author = {Anirban Sengupta and
Sandip Kundu},
title = {Guest Editorial Securing IoT Hardware: Threat Models and Reliable,
Low-Power Design Solutions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3265--3267},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2762398},
doi = {10.1109/TVLSI.2017.2762398},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SenguptaK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeoF017,
author = {Yeongkyo Seo and
Xuanyao Fong and
Kaushik Roy},
title = {Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer
{MTJ}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1573--1577},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2631981},
doi = {10.1109/TVLSI.2016.2631981},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeoF017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeoLKLHK17,
author = {JaeHyun Seo and
Sangheon Lee and
Kwangmin Kim and
Sooeun Lee and
Hyunsang Hwang and
Byungsub Kim},
title = {Automatic ReRAM {SPICE} Model Generation From Empirical Data for Fast
ReRAM-Circuit Coevaluation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1821--1830},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2655730},
doi = {10.1109/TVLSI.2017.2655730},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeoLKLHK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeokKCP17,
author = {Moon Gi Seok and
Tag Gon Kim and
Chang Beom Choi and
Daejin Park},
title = {An HLA-Based Distributed Cosimulation Framework in Mixed-Signal System-on-Chip
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {760--764},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2594948},
doi = {10.1109/TVLSI.2016.2594948},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeokKCP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeolSJCSK17,
author = {Hoseok Seol and
Wongyu Shin and
Jaemin Jang and
Jungwhan Choi and
Jinwoong Suh and
Lee{-}Sup Kim},
title = {In-DRAM Data Initialization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3251--3254},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2737646},
doi = {10.1109/TVLSI.2017.2737646},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeolSJCSK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeongLKSP17,
author = {Kihwan Seong and
Won{-}Cheol Lee and
Byungsub Kim and
Jae{-}Yoon Sim and
Hong{-}June Park},
title = {All-Synthesizable Current-Mode Transmitter Driver for {USB2.0} Interface},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {788--792},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2600267},
doi = {10.1109/TVLSI.2016.2600267},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeongLKSP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShaoHCCX17,
author = {Qiliang Shao and
Zhenji Hu and
Shaobo Chen and
Pingxiuqi Chen and
Jiafeng Xie},
title = {Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2817--2827},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2720190},
doi = {10.1109/TVLSI.2017.2720190},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShaoHCCX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SheikhEES17,
author = {Ahmad T. Sheikh and
Aiman H. El{-}Maleh and
Muhammad E. S. Elrabaa and
Sadiq M. Sait},
title = {A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor
Redundancy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {224--237},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2569532},
doi = {10.1109/TVLSI.2016.2569532},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SheikhEES17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenRSXTF17,
author = {Hao{-}Ting Shen and
Fahim Rahman and
Bicky Shakya and
Xiaolin Xu and
Mark M. Tehranipoor and
Domenic Forte},
title = {Poly-Si-Based Physical Unclonable Functions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3207--3217},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2733531},
doi = {10.1109/TVLSI.2017.2733531},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenRSXTF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiLYO17,
author = {Weijing Shi and
Xin Li and
Zhiyi Yu and
Gary Overett},
title = {An FPGA-Based Hardware Accelerator for Traffic Sign Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1362--1372},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2631428},
doi = {10.1109/TVLSI.2016.2631428},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiLYO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShimCS17,
author = {Seongbo Shim and
Woohyun Chung and
Youngsoo Shin},
title = {Lithography Defect Probability and Its Application to Physical Design
Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {271--285},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2572224},
doi = {10.1109/TVLSI.2016.2572224},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShimCS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongLHK17,
author = {Junyoung Song and
Hyun{-}Woo Lee and
Sewook Hwang and
Chulwoo Kim},
title = {A 10 Gbits/s/pin DFE-Less Graphics {DRAM} Interface With Adaptive-Bandwidth
{PLL} for Avoiding Noise Interference and {CIJ} Reduction Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {344--353},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2580713},
doi = {10.1109/TVLSI.2016.2580713},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongLHK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongWHLCL17,
author = {Lili Song and
Ying Wang and
Yinhe Han and
Huawei Li and
Yuanqing Cheng and
Xiaowei Li},
title = {{STT-RAM} Buffer Design for Precision-Tunable General-Purpose Neural
Network Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1285--1296},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2644279},
doi = {10.1109/TVLSI.2016.2644279},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SongWHLCL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunLCCCCY17,
author = {Xiaoyu Sun and
Rui Liu and
Yi{-}Ju Chen and
Hsiao{-}Yun Chiu and
Wei{-}Hao Chen and
Meng{-}Fan Chang and
Shimeng Yu},
title = {Low-VDD Operation of {SRAM} Synaptic Array for Implementing Ternary
Neural Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2962--2965},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2727528},
doi = {10.1109/TVLSI.2017.2727528},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunLCCCCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TaatizadehN17,
author = {Pouya Taatizadeh and
Nicola Nicolici},
title = {Emulation Infrastructure for the Evaluation of Hardware Assertions
for Post-Silicon Validation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1866--1880},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2658564},
doi = {10.1109/TVLSI.2017.2658564},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TaatizadehN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Taherzadeh-Sani17,
author = {Mohammad Taherzadeh{-}Sani and
Said M. Hussain Hussaini and
Hamidreza Rezaee{-}Dehsorkh and
Frederic Nabki and
Mohamad Sawan},
title = {A 170-dB {\(\Omega\)} {CMOS} {TIA} With 52-pA Input-Referred Noise
and 1-MHz Bandwidth for Very Low Current Sensing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1756--1766},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2654452},
doi = {10.1109/TVLSI.2017.2654452},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Taherzadeh-Sani17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TehranipoorKYC17,
author = {Fatemeh Tehranipoor and
Nima Karimian and
Wei Yan and
John A. Chandy},
title = {DRAM-Based Intrinsic Physically Unclonable Functions for System-Level
Security and Authentication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1085--1097},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2606658},
doi = {10.1109/TVLSI.2016.2606658},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TehranipoorKYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TenentesRYKAG17,
author = {Vasileios Tenentes and
Daniele Rossi and
Sheng Yang and
S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
Steve R. Gunn},
title = {Coarse-Grained Online Monitoring of {BTI} Aging by Reusing Power-Gating
Infrastructure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1397--1407},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2626218},
doi = {10.1109/TVLSI.2016.2626218},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TenentesRYKAG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TohidianMS17,
author = {Massoud Tohidian and
Iman Madadi and
Robert Bogdan Staszewski},
title = {A Fully Integrated Discrete-Time Superheterodyne Receiver},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {635--647},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2598857},
doi = {10.1109/TVLSI.2016.2598857},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TohidianMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TongZMLLZL17,
author = {Yufeng Tong and
Wei Zhang and
Yung{-}Cheng Ma and
Yanyan Liu and
Yu Liang and
Tai Zhang and
Haowen Luo},
title = {Compiler-Guided Parallelism Adaption Based on Application Partition
for Power-Gated {ILP} Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1329--1341},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2636419},
doi = {10.1109/TVLSI.2016.2636419},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TongZMLLZL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TorresV17,
author = {Vicente Torres and
Javier Valls},
title = {A Fast and Low-Complexity Operator for the Computation of the Arctangent
of a Complex Number},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2663--2667},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2700519},
doi = {10.1109/TVLSI.2017.2700519},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TorresV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TossonYAW17,
author = {Amr M. S. Tosson and
Shimeng Yu and
Mohab H. Anis and
Lan Wei},
title = {A Study of the Effect of {RRAM} Reliability Soft Errors on the Performance
of RRAM-Based Neuromorphic Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3125--3137},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2734819},
doi = {10.1109/TVLSI.2017.2734819},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TossonYAW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiCPTCZCC17,
author = {Hsiang{-}Jen Tsai and
Chien{-}Chih Chen and
Yin{-}Chi Peng and
Ya{-}Han Tsao and
Yen{-}Ning Chiang and
Wei{-}Cheng Zhao and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous
Discrete Finite Automata},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3302--3316},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2671408},
doi = {10.1109/TVLSI.2017.2671408},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiCPTCZCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiYPLTCC17,
author = {Hsiang{-}Jen Tsai and
Keng{-}Hao Yang and
Yin{-}Chi Peng and
Chien{-}Chen Lin and
Ya{-}Han Tsao and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {Energy-Efficient {TCAM} Search Engine Design Using Priority-Decision
in Memory Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {962--973},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2624990},
doi = {10.1109/TVLSI.2016.2624990},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiYPLTCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TuYOTLW17,
author = {Fengbin Tu and
Shouyi Yin and
Peng Ouyang and
Shibin Tang and
Leibo Liu and
Shaojun Wei},
title = {Deep Convolutional Neural Network Architecture With Reconfigurable
Computation Patterns},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2220--2233},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2688340},
doi = {10.1109/TVLSI.2017.2688340},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TuYOTLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VK17,
author = {Mohammed Zackriya V and
Harish M. Kittur},
title = {Content Addressable Memory - Early Predict and Terminate Precharge
of Match-Line},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {385--387},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2576281},
doi = {10.1109/TVLSI.2016.2576281},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ValeroMPSJ17,
author = {Alejandro Valero and
Negar Miralaei and
Salvador Petit and
Julio Sahuquillo and
Timothy M. Jones},
title = {On Microarchitectural Mechanisms for Cache Wearout Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {857--871},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2625809},
doi = {10.1109/TVLSI.2016.2625809},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ValeroMPSJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VelampatiHHJ17,
author = {Ravi Shankar R. Velampati and
El{-}Sayed A. M. Hasaneen and
E. K. Heller and
Faquir C. Jain},
title = {Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed
Quantum Dots},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1774--1781},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2645795},
doi = {10.1109/TVLSI.2016.2645795},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VelampatiHHJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VenkatachalamK17,
author = {Suganthi Venkatachalam and
Seok{-}Bum Ko},
title = {Design of Power and Area Efficient Approximate Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1782--1786},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2643639},
doi = {10.1109/TVLSI.2016.2643639},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VenkatachalamK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCTLTLSLWC17,
author = {Po{-}Hao Wang and
Yung{-}Chen Chien and
Shang{-}Jen Tsai and
Xuan{-}Yu Lin and
Rizal Tanjung and
Yi{-}Sian Lin and
Shu{-}Wei Syu and
Tay{-}Jyi Lin and
Jinn{-}Shyan Wang and
Tien{-}Fu Chen},
title = {ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric
Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3341--3354},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2642170},
doi = {10.1109/TVLSI.2016.2642170},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCTLTLSLWC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCXM17,
author = {Sheng Wang and
Chen Chen and
Xiaoyan Xiang and
Jian{-}Yi Meng},
title = {A Variation-Tolerant Near-Threshold Processor With Instruction-Level
Error Correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {1993--2006},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2676026},
doi = {10.1109/TVLSI.2017.2676026},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCXM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangDFLL17,
author = {Ying Wang and
Jiachao Deng and
Yuntan Fang and
Huawei Li and
Xiaowei Li},
title = {Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate
Computing Chips},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2736--2748},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2682885},
doi = {10.1109/TVLSI.2017.2682885},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangDFLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangGBSS17,
author = {Zhiheng Wang and
Ryan N. Goh and
Kia Bazargan and
Arnd Scheel and
Naman Saraf},
title = {Stochastic Implementation and Analysis of Dynamical Systems Similar
to the Logistic Map},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {747--759},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2598359},
doi = {10.1109/TVLSI.2016.2598359},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangGBSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangKUKK17,
author = {Longfei Wang and
S. Karen Khatamifard and
Orhun Aras Uzun and
Ulya R. Karpuzcu and
Sel{\c{c}}uk K{\"{o}}se},
title = {Efficiency, Stability, and Reliability Implications of Unbalanced
Current Sharing Among Distributed On-Chip Voltage Regulators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3019--3032},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2742944},
doi = {10.1109/TVLSI.2017.2742944},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangKUKK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangL17,
author = {Mingyu Wang and
Zhaolin Li},
title = {A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network
Optimization for Tiled Many-Core Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2419--2433},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2712366},
doi = {10.1109/TVLSI.2017.2712366},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLW17,
author = {Zhisheng Wang and
Jun Lin and
Zhongfeng Wang},
title = {Accelerating Recurrent Neural Networks: {A} Memory-Efficient Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2763--2775},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2717950},
doi = {10.1109/TVLSI.2017.2717950},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangPHZ17,
author = {Ze{-}ke Wang and
Johns Paul and
Bingsheng He and
Wei Zhang},
title = {Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1906--1918},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2653818},
doi = {10.1109/TVLSI.2017.2653818},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangPHZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangS17,
author = {Hailang Wang and
Emre Salman},
title = {Closed-Form Expressions for {I/O} Simultaneous Switching Noise Revisited},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {769--773},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2584387},
doi = {10.1109/TVLSI.2016.2584387},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangT17,
author = {Shengcheng Wang and
Mehdi Baradaran Tahoori},
title = {Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of
3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2881--2892},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2716821},
doi = {10.1109/TVLSI.2017.2716821},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangTC17,
author = {Dong Wang and
Xiao Liang Tan and
Pak Kwong Chan},
title = {A 65-nm {CMOS} Constant Current Source With Reduced {PVT} Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1373--1385},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2633566},
doi = {10.1109/TVLSI.2016.2633566},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangTC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangW17,
author = {Jinn{-}Shyan Wang and
Shih{-}Nung Wei},
title = {Process/Voltage/Temperature-Variation-Aware Design and Comparative
Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient
Pipelined Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2893--2906},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2723020},
doi = {10.1109/TVLSI.2017.2723020},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangY17,
author = {Fengjuan Wang and
Ningmei Yu},
title = {An Ultracompact Butterworth Low-Pass Filter Based on Coaxial Through-Silicon
Vias},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1164--1167},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2620460},
doi = {10.1109/TVLSI.2016.2620460},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangYLZZ17,
author = {Mengshuo Wang and
Changhao Yan and
Xin Li and
Dian Zhou and
Xuan Zeng},
title = {High-Dimensional and Multiple-Failure-Region Importance Sampling for
{SRAM} Yield Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {806--819},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2601606},
doi = {10.1109/TVLSI.2016.2601606},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangYLZZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WaryM17,
author = {Nijwm Wary and
Pradip Mandal},
title = {Current-Mode Triline Transceiver for Coded Differential Signaling
Across On-Chip Global Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2575--2587},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2707535},
doi = {10.1109/TVLSI.2017.2707535},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WaryM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuLCH17,
author = {Chung{-}Shiang Wu and
Hui{-}Hsuan Lee and
Po{-}Hung Chen and
Wei Hwang},
title = {Digital Buck Converter With Switching Loss Reduction Scheme for Light
Load Efficiency Enhancement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {783--787},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2592537},
doi = {10.1109/TVLSI.2016.2592537},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuLCH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuLZLHXY17,
author = {Tongda Wu and
Yongpan Liu and
Daming Zhang and
Jinyang Li and
Xiaobo Sharon Hu and
Chun Jason Xue and
Huazhong Yang},
title = {DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered
Sensor Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {2981--2994},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2736552},
doi = {10.1109/TVLSI.2017.2736552},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuLZLHXY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuNZLCLL17,
author = {Liang Wu and
Alan W. L. Ng and
Shiyuan Zheng and
Hiu Fai Leung and
Yue Chao and
Alvin Li and
Howard C. Luong},
title = {A 0.9-5.8-GHz Software-Defined Receiver {RF} Front-End With Transformer-Based
Current-Gain Boosting and Harmonic Rejection Calibration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2371--2382},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2695719},
doi = {10.1109/TVLSI.2017.2695719},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuNZLCLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaWXY17,
author = {Kaifeng Xia and
Bin Wu and
Tao Xiong and
Tian{-}Chun Ye},
title = {A Memory-Based {FFT} Processor Design With Generalized Efficient Conflict-Free
Address Schemes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1919--1929},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2666820},
doi = {10.1109/TVLSI.2017.2666820},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaWXY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiangWW17,
author = {Dong Xiang and
Xiaoqing Wen and
Laung{-}Terng Wang},
title = {Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom
Test Pattern Generation and Reseeding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {942--953},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2606248},
doi = {10.1109/TVLSI.2016.2606248},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiangWW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaoBS17,
author = {Zhekai Xiao and
Anh Khoa Bui and
Liter Siek},
title = {A Hysteretic Switched-Capacitor {DC-DC} Converter With Optimal Output
Ripple and Fast Transient Response},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {2995--3005},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2728606},
doi = {10.1109/TVLSI.2017.2728606},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaoBS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XingZCSYRUM17,
author = {Dezhi Xing and
Yan Zhu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Fan Ye and
Junyan Ren and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Seven-bit 700-MS/s Four-Way Time-Interleaved {SAR} {ADC} With Partial
{\textdollar}V{\_}\{{\textbackslash}mathrm \{cm\}\}{\textdollar} -Based
Switching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1168--1172},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2610864},
doi = {10.1109/TVLSI.2016.2610864},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XingZCSYRUM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuS17,
author = {Siyuan Xu and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer},
title = {Exposing Approximate Computing Optimizations at Different Levels:
From Behavioral to Gate-Level},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3077--3088},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2735299},
doi = {10.1109/TVLSI.2017.2735299},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuZWC17,
author = {Yang Xu and
Xinwang Zhang and
Zhihua Wang and
Baoyong Chi},
title = {A Flexible Continuous-Time {\(\Delta\)} {\(\Sigma\)} {ADC} With Programmable
Bandwidth Supporting Low-Pass and Complex Bandpass Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {872--880},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2611518},
doi = {10.1109/TVLSI.2016.2611518},
timestamp = {Fri, 23 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuZWC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanHYXOL17,
author = {Aibin Yan and
Zhengfeng Huang and
Maoxiang Yi and
Xiumin Xu and
Yiming Ouyang and
Huaguo Liang},
title = {Double-Node-Upset-Resilient Latch Design for Nanoscale {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1978--1982},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2655079},
doi = {10.1109/TVLSI.2017.2655079},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanHYXOL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanYLLW17,
author = {Jian Yan and
Junqi Yuan and
Philip Heng Wai Leong and
Wayne Luk and
Lingli Wang},
title = {Lossless Compression Decoders for Bitstreams and Software Binaries
Based on High-Level Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2842--2855},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2713527},
doi = {10.1109/TVLSI.2017.2713527},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanYLLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangJC17,
author = {Isaak Yang and
Sung Hoon Jung and
Kwang{-}Hyun Cho},
title = {Self-Repairing Digital System Based on State Attractor Convergence
Inspired by the Recovery Process of a Living Cell},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {648--659},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2593482},
doi = {10.1109/TVLSI.2016.2593482},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangJC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YaoB17,
author = {Enyi Yao and
Arindam Basu},
title = {{VLSI} Extreme Learning Machine: {A} Design Space Exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {60--74},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2558842},
doi = {10.1109/TVLSI.2016.2558842},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YaoB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YongXCM17,
author = {Zhenqiang Yong and
Xiaoyan Xiang and
Chen Chen and
Jianyi Meng},
title = {An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual
Current Mirror},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3534--3538},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2748228},
doi = {10.1109/TVLSI.2017.2748228},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YongXCM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YounKSPK17,
author = {Yelim Youn and
Kwangmin Kim and
Jae{-}Yoon Sim and
Hong{-}June Park and
Byungsub Kim},
title = {Investigation on the Worst Read Scenario of a ReRAM Crossbar Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2402--2410},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2710140},
doi = {10.1109/TVLSI.2017.2710140},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YounKSPK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuK17,
author = {Weize Yu and
Sel{\c{c}}uk K{\"{o}}se},
title = {Security-Adaptive Voltage Conversion as a Lightweight Countermeasure
Against {LPA} Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2183--2187},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2670537},
doi = {10.1109/TVLSI.2017.2670537},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuanLLHXY17,
author = {Zhe Yuan and
Yongpan Liu and
Jinyang Li and
Jingtong Hu and
Chun Jason Xue and
Huazhong Yang},
title = {{CP-FPGA:} Energy-Efficient Nonvolatile {FPGA} With Offline/Online
Checkpointing Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2153--2163},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2680464},
doi = {10.1109/TVLSI.2017.2680464},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuanLLHXY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuanLTHCAX17,
author = {Luechao Yuan and
Cang Liu and
Chuan Tang and
Shan Huang and
Anupam Chattopadhyay and
Gerd Ascheid and
Zuocheng Xing},
title = {A Flexible Divide-and-Conquer MPSoC Architecture for {MIMO} Interference
Cancellation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2789--2802},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2728609},
doi = {10.1109/TVLSI.2017.2728609},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuanLTHCAX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuanW17,
author = {Wen Yuan and
Jeffrey S. Walling},
title = {A Switched-Capacitor-Controlled Digital-Current Modulated Class-E
Transmitter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3218--3226},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2736889},
doi = {10.1109/TVLSI.2017.2736889},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuanW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZahraiZDO17,
author = {Seyed Alireza Zahrai and
Marina Zlochisti and
Nicolas Le Dortz and
Marvin Onabajo},
title = {A Low-Power High-Speed Hybrid {ADC} With Merged Sample-and-Hold and
{DAC} Functions for Efficient Subranging Time-Interleaved Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3193--3206},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2739108},
doi = {10.1109/TVLSI.2017.2739108},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZahraiZDO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZamanlooyM17,
author = {Babak Zamanlooy and
Mitra Mirhassani},
title = {An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {894--906},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2615306},
doi = {10.1109/TVLSI.2016.2615306},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZamanlooyM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZandRD17,
author = {Ramtin Zand and
Arman Roohi and
Ronald F. DeMara},
title = {Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes
for Spin Hall Effect {MRAM} Device},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2394--2401},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2699579},
doi = {10.1109/TVLSI.2017.2699579},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZandRD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZarandiMSH17,
author = {Azadeh Alsadat Emrani Zarandi and
Amir Sabbagh Molahosseini and
Leonel Sousa and
Mehdi Hosseinzadeh},
title = {An Efficient Component for Designing Signed Reverse Converters for
a Class of {RNS} Moduli Sets of Composite Form \{2\({}^{\mbox{k}}\),
2\({}^{\mbox{P}}\)-1\}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {48--59},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2577609},
doi = {10.1109/TVLSI.2016.2577609},
timestamp = {Thu, 12 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZarandiMSH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZendeganiKBAP17,
author = {Reza Zendegani and
Mehdi Kamal and
Milad Bahadori and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {RoBA Multiplier: {A} Rounding-Based Approximate Multiplier for High-Speed
yet Energy-Efficient Digital Signal Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {393--401},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2587696},
doi = {10.1109/TVLSI.2016.2587696},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZendeganiKBAP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangCGMHZC17,
author = {Xinwang Zhang and
Zipeng Chen and
Yanqiang Gao and
Feng Ma and
Jiachen Hao and
Guodong Zhu and
Baoyong Chi},
title = {An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated
{LNA} in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3113--3124},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2736003},
doi = {10.1109/TVLSI.2017.2736003},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangCGMHZC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangL17,
author = {Jiliang Zhang and
Lele Liu},
title = {Publicly Verifiable Watermarking for Intellectual Property Protection
in {FPGA} Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1520--1527},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2619682},
doi = {10.1109/TVLSI.2016.2619682},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangLFW17,
author = {Zhao Zhang and
Liyuan Liu and
Peng Feng and
Nanjian Wu},
title = {A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked {PLL} With
Adaptive Injection Timing Alignment Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {929--941},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2619362},
doi = {10.1109/TVLSI.2016.2619362},
timestamp = {Mon, 18 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangLFW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangS17,
author = {Xiang Zhang and
Liter Siek},
title = {An 80.4{\%} Peak Power Efficiency Adaptive Supply Class {H} Power
Amplifier for Audio Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1954--1965},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2666268},
doi = {10.1109/TVLSI.2017.2666268},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangSGNW17,
author = {Guangda Zhang and
Wei Song and
Jim D. Garside and
Javier Navaridas and
Zhiying Wang},
title = {Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive
Networks-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {11},
pages = {3152--3165},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2729081},
doi = {10.1109/TVLSI.2017.2729081},
timestamp = {Thu, 25 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangSGNW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangT17,
author = {Xinmiao Zhang and
Ying Tai},
title = {Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic
Nonbinary {LDPC} Codes Over Subfields},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1342--1351},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2630055},
doi = {10.1109/TVLSI.2016.2630055},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWZZ17,
author = {Yiping Zhang and
Ziou Wang and
Canyan Zhu and
Lijun Zhang},
title = {28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1767--1773},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2649886},
doi = {10.1109/TVLSI.2017.2649886},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWZZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangZ17,
author = {Bin Zhang and
Jizhong Zhao},
title = {Hardware Implementation for Real-Time Haze Removal},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {1188--1192},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2622404},
doi = {10.1109/TVLSI.2016.2622404},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoYLFL17,
author = {Chenyuan Zhao and
Yang Yi and
Jialing Li and
Xin Fu and
Lingjia Liu},
title = {Interspike-Interval-Based Analog Spike-Time-Dependent Encoder for
Neuromorphic Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2193--2205},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2683260},
doi = {10.1109/TVLSI.2017.2683260},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoYLFL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoZLL17,
author = {Yizhi Zhao and
Xuecheng Zou and
Zhaojun Lu and
Zhenglin Liu},
title = {Chaotic Encrypted Polar Coding Scheme for General Wiretap Channel},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3331--3340},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2636908},
doi = {10.1109/TVLSI.2016.2636908},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoZLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouZWZYG17,
author = {Jian{-}Bin Zhou and
Dajiang Zhou and
Shihao Wang and
Shuping Zhang and
Takeshi Yoshimura and
Satoshi Goto},
title = {A Dual-Clock {VLSI} Design of {H.265} Sample Adaptive Offset Estimation
for 8k Ultra-HD {TV} Encoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {714--724},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2593581},
doi = {10.1109/TVLSI.2016.2593581},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouZWZYG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuMXY17,
author = {Tao{-}Tao Zhu and
Jian{-}Yi Meng and
Xiaoyan Xiang and
Xiaolang Yan},
title = {Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization
on a Wide Voltage {IOT} Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {5},
pages = {1681--1693},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2652482},
doi = {10.1109/TVLSI.2017.2652482},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuMXY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZouKX17,
author = {Qiaosha Zou and
Eren Kursun and
Yuan Xie},
title = {Thermomechanical Stress-Aware Management for 3-D {IC} Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {9},
pages = {2678--2682},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2707119},
doi = {10.1109/TVLSI.2017.2707119},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZouKX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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