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@article{DBLP:journals/tvlsi/AliotoP02,
author = {Massimo Alioto and
Gaetano Palumbo},
title = {Analysis and comparison on full adder block in submicron technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {806--823},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808446},
doi = {10.1109/TVLSI.2002.808446},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliotoP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlupoaeiK02,
author = {Stelian Alupoaei and
Srinivas Katkoori},
title = {Net-based force-directed macrocell placement for wirelength optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {824--835},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808453},
doi = {10.1109/TVLSI.2002.808453},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlupoaeiK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AnisAE02,
author = {Mohab Anis and
Mohamed W. Allam and
Mohamed I. Elmasry},
title = {Energy-efficient noise-tolerant dynamic styles for scaled-down {CMOS}
and {MTCMOS} technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {71--78},
year = {2002},
url = {https://doi.org/10.1109/92.994977},
doi = {10.1109/92.994977},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AnisAE02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeattieP02,
author = {Michael W. Beattie and
Lawrence T. Pileggi},
title = {On-chip induction modeling: basics and advanced methods},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {712--729},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2003.808682},
doi = {10.1109/TVLSI.2003.808682},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BeattieP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeniniMMP02,
author = {Luca Benini and
Luca Macchiarulo and
Alberto Macii and
Massimo Poncino},
title = {Layout-driven memory synthesis for embedded systems-on-chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {96--105},
year = {2002},
url = {https://doi.org/10.1109/92.994985},
doi = {10.1109/92.994985},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BeniniMMP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeniniMMP02a,
author = {Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Minimizing memory access energy in embedded systems by selective instruction
compression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {521--531},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801615},
doi = {10.1109/TVLSI.2002.801615},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BeniniMMP02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BrewerH02,
author = {Forrest Brewer and
Steve Haynal},
title = {Symbolic {NFA} scheduling of a {RISC} microprocessor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {429--434},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.807349},
doi = {10.1109/TVLSI.2002.807349},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BrewerH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoHCLNXSH02,
author = {Yu Cao and
Xuejue Huang and
N. H. Chang and
Shen Lin and
O. Sam Nakagawa and
Weize Xie and
Dennis Sylvester and
Chenming Hu},
title = {Effective on-chip inductance modeling for multiple signal lines and
application to repeater insertion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {799--805},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808426},
doi = {10.1109/TVLSI.2002.808426},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoHCLNXSH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangK02,
author = {You{-}Sung Chang and
Chong{-}Min Kyung},
title = {Conforming block inversion for low power memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {15--19},
year = {2002},
url = {https://doi.org/10.1109/92.988726},
doi = {10.1109/92.988726},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangKL02,
author = {Naehyuck Chang and
Kwanho Kim and
Hyung Gyu Lee},
title = {Cycle-accurate energy measurement and characterization with a case
study of the {ARM7TDMI} [microprocessors]},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {146--154},
year = {2002},
url = {https://doi.org/10.1109/92.994992},
doi = {10.1109/92.994992},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangKL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChathaV02,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {Hardware-software partitioning and pipelined scheduling of transformative
applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {193--208},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043323},
doi = {10.1109/TVLSI.2002.1043323},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChathaV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenSW02,
author = {Oscal T.{-}C. Chen and
Robin R.{-}B. Sheen and
S. Wang},
title = {A low-power adder operating on effective dynamic data ranges},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {435--453},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2003.809138},
doi = {10.1109/TVLSI.2003.809138},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenSW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenZA02,
author = {Chunhong Chen and
Jiang Zhao and
Majid Ahmadi},
title = {Probability-based approach to rectilinear Steiner tree problems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {836--843},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808463},
doi = {10.1109/TVLSI.2002.808463},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenZA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengKLS02,
author = {Chung{-}Kuan Cheng and
Andrew B. Kahng and
Bao Liu and
Dirk Stroobandt},
title = {Toward better wireload models in the presence of obstacles},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {177--189},
year = {2002},
url = {https://doi.org/10.1109/92.994997},
doi = {10.1109/92.994997},
timestamp = {Thu, 21 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengKLS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengP02,
author = {Wei{-}Chung Cheng and
Massoud Pedram},
title = {Power-optimal encoding for a {DRAM} address bus},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {109--118},
year = {2002},
url = {https://doi.org/10.1109/92.994988},
doi = {10.1109/92.994988},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChungLS02,
author = {Wai Chung and
Timothy Lo and
Manoj Sachdev},
title = {A comparative analysis of low-power low-voltage dual-edge-triggered
flip-flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {913--918},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808429},
doi = {10.1109/TVLSI.2002.808429},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChungLS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ComptonLCKH02,
author = {Katherine Compton and
Zhiyuan Li and
James Cooley and
Stephen Knol and
Scott Hauck},
title = {Configuration relocation and defragmentation for run-time reconfigurable
computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {209--220},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043324},
doi = {10.1109/TVLSI.2002.1043324},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ComptonLCKH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DebonoMM02,
author = {Carl James Debono and
Franco Maloberti and
Joseph Micallef},
title = {On the design of low-voltage, low-power {CMOS} analog multipliers
for {RF} applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {168--174},
year = {2002},
url = {https://doi.org/10.1109/92.994995},
doi = {10.1109/92.994995},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DebonoMM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuarteVI02,
author = {D. E. Duarte and
Narayanan Vijaykrishnan and
Mary Jane Irwin},
title = {A clock power model to evaluate impact of architectural and technology
optimizations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {844--855},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808433},
doi = {10.1109/TVLSI.2002.808433},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DuarteVI02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FallahAD02,
author = {Farzan Fallah and
Pranav Ashar and
Srinivas Devadas},
title = {Functional vector generation for sequential {HDL} models under an
observability-based code coverage metric},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {919--923},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808438},
doi = {10.1109/TVLSI.2002.808438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FallahAD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GalaBZVJ02,
author = {Kaushik Gala and
David T. Blaauw and
Vladimir Zolotov and
Pravin M. Vaidya and
Anil Joshi},
title = {Inductance model and analysis methodology for high-speed on-chip interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {730--745},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801619},
doi = {10.1109/TVLSI.2002.801619},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GalaBZVJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Gebotys02,
author = {Catherine H. Gebotys},
title = {A network flow approach to memory bandwidth utilization in embedded
{DSP} core processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {390--398},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.807766},
doi = {10.1109/TVLSI.2002.807766},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Gebotys02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GivargisVH02,
author = {Tony Givargis and
Frank Vahid and
J{\"{o}}rg Henkel},
title = {System-level exploration for Pareto-optimal configurations in parameterized
system-on-a-chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {416--422},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.807764},
doi = {10.1109/TVLSI.2002.807764},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GivargisVH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GivargisVH02a,
author = {Tony Givargis and
Frank Vahid and
J{\"{o}}rg Henkel},
title = {Instruction-based system-level power evaluation of system-on-a-chip
peripheral cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {856--863},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808443},
doi = {10.1109/TVLSI.2002.808443},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GivargisVH02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HamzaogluYKZNBSD02,
author = {Fatih Hamzaoglu and
Yibin Ye and
Ali Keshavarzi and
Kevin Zhang and
Siva G. Narendra and
Shekhar Borkar and
Mircea R. Stan and
Vivek De},
title = {Analysis of dual-V\({}_{\mbox{T}}\) {SRAM} cells with full-swing single-ended
bit line sensing for on-chip cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {91--95},
year = {2002},
url = {https://doi.org/10.1109/92.994983},
doi = {10.1109/92.994983},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HamzaogluYKZNBSD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HenkelL02,
author = {J{\"{o}}rg Henkel and
Yanbing Li},
title = {Avalanche: an environment for design space exploration and optimization
of low-power embedded systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {454--468},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800524},
doi = {10.1109/TVLSI.2002.800524},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HenkelL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoyerYS02,
author = {Gregg N. Hoyer and
Gin Yee and
Carl Sechen},
title = {Locally clocked pipelines and dynamic logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {58--62},
year = {2002},
url = {https://doi.org/10.1109/92.988731},
doi = {10.1109/92.988731},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HoyerYS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuS02,
author = {Haitian Hu and
Sachin S. Sapatnekar},
title = {Efficient inductance extraction using circuit-aware techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {746--761},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808455},
doi = {10.1109/TVLSI.2002.808455},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangX02,
author = {Ing{-}Jer Huang and
Ping{-}Huei Xie},
title = {Application of instruction analysis/scheduling techniques to resource
allocation of superscalar processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {44--54},
year = {2002},
url = {https://doi.org/10.1109/92.988729},
doi = {10.1109/92.988729},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangX02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ImR02,
author = {Yonghee Im and
Kaushik Roy},
title = {O\({}^{\mbox{2}}\)ABA: a novel high-performance predictable circuit
architecture for the deep submicron era},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {221--229},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043325},
doi = {10.1109/TVLSI.2002.1043325},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ImR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Ismail02,
author = {Yehea I. Ismail},
title = {On-chip inductance cons and pros},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {685--694},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808445},
doi = {10.1109/TVLSI.2002.808445},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Ismail02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IsmailK02,
author = {Yehea I. Ismail and
Byron Krauter},
title = {Guest editorial: special issue on on-chip inductance in high-speed
integrated circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {683--684},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2003.808778},
doi = {10.1109/TVLSI.2003.808778},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IsmailK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IyerM02,
author = {Anoop Iyer and
Diana Marculescu},
title = {Microarchitecture-level power management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {230--239},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043326},
doi = {10.1109/TVLSI.2002.1043326},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IyerM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JinLS02,
author = {Zhong{-}Fang Jin and
Jean{-}Jacques Laurin and
Yvon Savaria},
title = {A practical approach to model long {MIS} interconnects in {VLSI} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {494--507},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800520},
doi = {10.1109/TVLSI.2002.800520},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JinLS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JohnsonSCR02,
author = {Mark C. Johnson and
Dinesh Somasekhar and
Lih{-}Yih Chiou and
Kaushik Roy},
title = {Leakage control with efficient use of transistor stacks in single
threshold {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {1--5},
year = {2002},
url = {https://doi.org/10.1109/92.988724},
doi = {10.1109/92.988724},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JohnsonSCR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoneHWL02,
author = {Wen{-}Ben Jone and
Der{-}Cheng Huang and
S. C. Wu and
Kuen{-}Jong Lee},
title = {An efficient {BIST} method for distributed small buffers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {512--515},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800532},
doi = {10.1109/TVLSI.2002.800532},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoneHWL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JouKSC02,
author = {Jer{-}Min Jou and
Shiann{-}Rong Kuang and
Yeu{-}Horng Shiau and
Ren{-}Der Chen},
title = {Design of a dynamic pipelined architecture for fuzzy color correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {924--929},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808458},
doi = {10.1109/TVLSI.2002.808458},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JouKSC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JungKK02,
author = {Seong{-}Ook Jung and
Ki{-}Wook Kim and
Sung{-}Mo Kang},
title = {Noise constrained transistor sizing and power optimization for dual
Vs\({}_{\mbox{t}}\) domino logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {532--541},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801625},
doi = {10.1109/TVLSI.2002.801625},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JungKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JungLH02,
author = {Hyunuk Jung and
Kangnyoung Lee and
Soonhoi Ha},
title = {Efficient hardware controller synthesis for synchronous dataflow graph
in system level design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {423--428},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.807765},
doi = {10.1109/TVLSI.2002.807765},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JungLH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarriW02,
author = {Ramesh Karri and
Kaijie Wu},
title = {Algorithm level re-computing using implementation diversity: a register
transfer level concurrent error detection technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {864--875},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808440},
doi = {10.1109/TVLSI.2002.808440},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KarriW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhouriJ02,
author = {Kamal S. Khouri and
Niraj K. Jha},
title = {Leakage power analysis and reduction during behavioral synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {876--885},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808436},
doi = {10.1109/TVLSI.2002.808436},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhouriJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimK02,
author = {Byoung{-}Woon Kim and
Chong{-}Min Kyung},
title = {Exploiting intellectual properties with imprecise design costs for
system-on-chip synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {240--252},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043327},
doi = {10.1109/TVLSI.2002.1043327},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimRH02,
author = {Dohyung Kim and
Chan{-}Eun Rhee and
Soonhoi Ha},
title = {Combined data-driven and event-driven scheduling technique for fast
distributed cosimulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {672--678},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801572},
doi = {10.1109/TVLSI.2002.801572},
timestamp = {Fri, 15 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimRH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KocanS02,
author = {Fatih Kocan and
Daniel G. Saab},
title = {Correction to "ATPG for combinational circuits on configurable hardware"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {374--374},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043340},
doi = {10.1109/TVLSI.2002.1043340},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KocanS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KopcsayKWDRS02,
author = {Gerard V. Kopcsay and
Byron Krauter and
David Widiger and
Alina Deutsch and
Barry J. Rubin and
Howard H. Smith},
title = {A comprehensive 2-D inductance modeling approach for {VLSI} interconnects:
frequency-dependent extraction and compact circuit model synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {695--711},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801574},
doi = {10.1109/TVLSI.2002.801574},
timestamp = {Wed, 25 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KopcsayKWDRS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Kurdahi02,
author = {Fadi J. Kurdahi},
title = {Guest editorial special issue on system synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {377--378},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.806919},
doi = {10.1109/TVLSI.2002.806919},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Kurdahi02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LajoloRDL02,
author = {Marcello Lajolo and
Anand Raghunathan and
Sujit Dey and
Luciano Lavagno},
title = {Cosimulation-based power estimation for system-on-chip design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {253--266},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043328},
doi = {10.1109/TVLSI.2002.1043328},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LajoloRDL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LauwersG02,
author = {Erik Lauwers and
Georges G. E. Gielen},
title = {Power estimation methods for analog circuits for architectural exploration
of integrated systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {155--162},
year = {2002},
url = {https://doi.org/10.1109/92.994993},
doi = {10.1109/92.994993},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LauwersG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeongL02,
author = {Philip Heng Wai Leong and
Ivan K. H. Leung},
title = {A microcoded elliptic curve processor using {FPGA} technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {550--559},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801608},
doi = {10.1109/TVLSI.2002.801608},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeongL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiW02,
author = {Jin{-}Fu Li and
Cheng{-}Wen Wu},
title = {Efficient {FFT} network testing and diagnosis schemes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {267--278},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043329},
doi = {10.1109/TVLSI.2002.1043329},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCC02,
author = {Jai{-}Ming Lin and
Hsin{-}Lung Chen and
Yao{-}Wen Chang},
title = {Arbitrarily shaped rectilinear module placement using the transitive
closure graph representation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {886--901},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808431},
doi = {10.1109/TVLSI.2002.808431},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinT02,
author = {Rung{-}Bin Lin and
Chi{-}Ming Tsai},
title = {Theoretical analysis of bus-invert coding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {929--934},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808456},
doi = {10.1109/TVLSI.2002.808456},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuBM02,
author = {Yung{-}Hsiang Lu and
Luca Benini and
Giovanni De Micheli},
title = {Power-aware operating systems for interactive systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {119--134},
year = {2002},
url = {https://doi.org/10.1109/92.994989},
doi = {10.1109/92.994989},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuBM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuL02,
author = {Chih{-}Wen Lu and
Chung{-}Len Lee},
title = {A low-power high-speed class-AB buffer amplifier for flat-panel-display
application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {163--168},
year = {2002},
url = {https://doi.org/10.1109/92.994994},
doi = {10.1109/92.994994},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaciiV02,
author = {Enrico Macii and
Ingrid Verbauwhede},
title = {Guest editorial: low-power electronics and design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {69--70},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.994976},
doi = {10.1109/TVLSI.2002.994976},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaciiV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ManzakC02,
author = {Ali Manzak and
Chaitali Chakrabarti},
title = {A low power scheduling scheme with resources operating at multiple
voltages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {6--14},
year = {2002},
url = {https://doi.org/10.1109/92.988725},
doi = {10.1109/92.988725},
timestamp = {Mon, 12 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ManzakC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaseraMPVZ02,
author = {Guido Masera and
Marco Mazza and
Gianluca Piccinini and
Fabrizio Viglione and
Maurizio Zamboni},
title = {Architectural strategies for low-power {VLSI} turbo decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {279--285},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043330},
doi = {10.1109/TVLSI.2002.1043330},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaseraMPVZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MasselosCGM02,
author = {Kostas Masselos and
Francky Catthoor and
Constantinos E. Goutis and
Hugo De Man},
title = {A systematic methodology for the application of data transfer and
storage optimizing code transformations for power consumption and
execution time reduction in realizations of multimedia algorithms
on programmable processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {515--518},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800530},
doi = {10.1109/TVLSI.2002.800530},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MasselosCGM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MassoudMKBMW02,
author = {Yehia Massoud and
Steve S. Majors and
Jamil Kawa and
Tareq Bustami and
Don MacMillen and
Jacob K. White},
title = {Managing on-chip inductive effects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {789--798},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.807763},
doi = {10.1109/TVLSI.2002.807763},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MassoudMKBMW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MassoudW02,
author = {Yehia Massoud and
Jacob K. White},
title = {Simulation and modeling of the effect of substrate conductivity on
coupling inductance and circuit crosstalk},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {286--291},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043331},
doi = {10.1109/TVLSI.2002.1043331},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MassoudW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MezhibaF02,
author = {Andrey V. Mezhiba and
Eby G. Friedman},
title = {Inductive properties of high-performance power distribution grids},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {762--776},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2003.808683},
doi = {10.1109/TVLSI.2003.808683},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MezhibaF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MonteiroO02,
author = {Jos{\'{e}} C. Monteiro and
Arlindo L. Oliveira},
title = {Implicit {FSM} decomposition applied to low-power design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {560--565},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801611},
doi = {10.1109/TVLSI.2002.801611},
timestamp = {Wed, 08 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MonteiroO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorgenshteinFW02,
author = {Arkadiy Morgenshtein and
Alexander Fish and
Israel A. Wagner},
title = {Gate-diffusion input {(GDI):} a power-efficient method for digital
combinatorial circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {566--581},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801578},
doi = {10.1109/TVLSI.2002.801578},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MorgenshteinFW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuhammadR02,
author = {Khurram Muhammad and
Kaushik Roy},
title = {Reduced computational redundancy implementation of {DSP} algorithms
using computation sharing vector scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {292--300},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043332},
doi = {10.1109/TVLSI.2002.1043332},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MuhammadR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuleGGM02,
author = {A. V. Mule and
Elias N. Glytsis and
Thomas K. Gaylord and
James D. Meindl},
title = {Electrical and optical clock distribution networks for gigascale microprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {582--594},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801604},
doi = {10.1109/TVLSI.2002.801604},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MuleGGM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MurugavelRCC02,
author = {Ashok K. Murugavel and
N. Ranganathan and
Ramamurti Chandramouli and
Srinath Chavali},
title = {Least-square estimation of average power in digital {CMOS} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {55--58},
year = {2002},
url = {https://doi.org/10.1109/92.988730},
doi = {10.1109/92.988730},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MurugavelRCC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NavarroN02,
author = {Jo{\~{a}}o Navarro Jr. and
Wilhelmus A. M. Van Noije},
title = {Extended {TSPC} structures with double input/output data throughput
for gigahertz {CMOS} circuit design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {301--308},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043333},
doi = {10.1109/TVLSI.2002.1043333},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NavarroN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NogueraB02,
author = {Juanjo Noguera and
Rosa M. Badia},
title = {{HW/SW} codesign techniques for dynamically reconfigurable architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {399--415},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801575},
doi = {10.1109/TVLSI.2002.801575},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NogueraB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NouraniP02,
author = {Mehrdad Nourani and
Christos A. Papachristou},
title = {False path exclusion in delay analysis of {RTL} structures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {30--43},
year = {2002},
url = {https://doi.org/10.1109/92.988728},
doi = {10.1109/92.988728},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NouraniP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OehlerGW02,
author = {Peter Oehler and
Christoph Grimm and
Klaus Waldschmidt},
title = {A methodology for system-level synthesis of mixed-signal applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {935--942},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801577},
doi = {10.1109/TVLSI.2002.801577},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OehlerGW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Olivieri02,
author = {Mauro Olivieri},
title = {Theoretical system-level limits of power dissipation reduction under
a performance constraint in {VLSI} microprocessor design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {595--600},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801549},
doi = {10.1109/TVLSI.2002.801549},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Olivieri02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OrtizK02,
author = {Rolando Ram{\'{\i}}rez Ortiz and
John P. Knight},
title = {Compatible cell connections for multifamily dynamic logic gates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {327--340},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043336},
doi = {10.1109/TVLSI.2002.1043336},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OrtizK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PangjunS02,
author = {Jatuchai Pangjun and
Sachin S. Sapatnekar},
title = {Low-power clock distribution using multiple voltages and reduced swings},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {309--318},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043334},
doi = {10.1109/TVLSI.2002.1043334},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PangjunS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PantPW02,
author = {Mondira Deb Pant and
Pankaj Pant and
D. Scott Wills},
title = {On-chip decoupling capacitor optimization using architectural level
prediction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {319--326},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043335},
doi = {10.1109/TVLSI.2002.1043335},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PantPW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PedramW02,
author = {Massoud Pedram and
Qing Wu},
title = {Battery-powered digital {CMOS} design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {601--607},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801566},
doi = {10.1109/TVLSI.2002.801566},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PedramW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PerriCC02,
author = {Stefania Perri and
Pasquale Corsonello and
Giuseppe Cocorullo},
title = {{VLSI} circuits for low-power high-speed asynchronous addition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {608--613},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801567},
doi = {10.1109/TVLSI.2002.801567},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PerriCC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QuP02,
author = {Gang Qu and
Miodrag Potkonjak},
title = {Techniques for energy-efficient communication pipeline design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {542--549},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800522},
doi = {10.1109/TVLSI.2002.800522},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QuP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RamprasadHN02,
author = {Sumant Ramprasad and
Ibrahim N. Hajj and
Farid N. Najm},
title = {A technique for Improving dual-output domino logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {508--511},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800521},
doi = {10.1109/TVLSI.2002.800521},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RamprasadHN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RuanNCLS02,
author = {Shanq{-}Jang Ruan and
Edwin Naroska and
Yen{-}Jen Chang and
Feipei Lai and
Uwe Schwiegelshohn},
title = {{ENPCO:} an entropy-based partition-codec algorithm to reduce power
for bipartition-codec architecture in pipelined circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {942--949},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808422},
doi = {10.1109/TVLSI.2002.808422},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RuanNCLS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SamiSSZZ02,
author = {Mariagiovanna Sami and
Donatella Sciuto and
Cristina Silvano and
Vittorio Zaccaria and
Roberto Zafalon},
title = {Low-power data forwarding for {VLIW} embedded architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {614--622},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801617},
doi = {10.1109/TVLSI.2002.801617},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SamiSSZZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchmidtCKTN02,
author = {Eike Schmidt and
Gerd von C{\"{o}}lln and
Lars Kruse and
Frans Theeuwen and
Wolfgang Nebel},
title = {Memory power models for multilevel power estimation and optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {106--109},
year = {2002},
url = {https://doi.org/10.1109/92.994987},
doi = {10.1109/92.994987},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SchmidtCKTN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShamsDB02,
author = {Ahmed M. Shams and
Tarek Darwish and
Magdy A. Bayoumi},
title = {Performance analysis of low-power 1-bit {CMOS} full adder cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {20--29},
year = {2002},
url = {https://doi.org/10.1109/92.988727},
doi = {10.1109/92.988727},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShamsDB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinhaWC02,
author = {Amit Sinha and
Alice Wang and
Anantha P. Chandrakasan},
title = {Energy scalable system design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {135--145},
year = {2002},
url = {https://doi.org/10.1109/92.994990},
doi = {10.1109/92.994990},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SinhaWC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SirichotiyakulEOPB02,
author = {Supamas Sirichotiyakul and
Tim Edwards and
Chanhee Oh and
Rajendran Panda and
David T. Blaauw},
title = {Duet: an accurate leakage estimation and optimization tool for dual-V\({}_{\mbox{t}}\)
circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {79--90},
year = {2002},
url = {https://doi.org/10.1109/92.994980},
doi = {10.1109/92.994980},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SirichotiyakulEOPB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SolomatnikovSSR02,
author = {Alexandre Solomatnikov and
Dinesh Somasekhar and
Naran Sirisantana and
Kaushik Roy},
title = {Skewed {CMOS:} noise-tolerant high-performance low-power static circuit
family},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {469--476},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800519},
doi = {10.1109/TVLSI.2002.800519},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SolomatnikovSSR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SotiriadisC02,
author = {Paul{-}Peter Sotiriadis and
Anantha P. Chandrakasan},
title = {A bus energy model for deep submicron technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {341--350},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043337},
doi = {10.1109/TVLSI.2002.1043337},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SotiriadisC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Stroobandt02,
author = {Dirk Stroobandt},
title = {Guest editorial - system-level interconnect prediction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {175--176},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.994996},
doi = {10.1109/TVLSI.2002.994996},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Stroobandt02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Svensson02,
author = {Christer Svensson},
title = {Electrical interconnects revitalized},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {777--788},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801624},
doi = {10.1109/TVLSI.2002.801624},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Svensson02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangF02,
author = {Kevin T. Tang and
Eby G. Friedman},
title = {Simultaneous switching noise in on-chip {CMOS} power distribution
networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {487--493},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800533},
doi = {10.1109/TVLSI.2002.800533},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TessierJ02,
author = {Russell Tessier and
Snigdha Jana},
title = {Incremental compilation for parallel logic verification systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {623--636},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801614},
doi = {10.1109/TVLSI.2002.801614},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TessierJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Touba02,
author = {Nur A. Touba},
title = {Circular {BIST} with state skipping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {668--672},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801564},
doi = {10.1109/TVLSI.2002.801564},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Touba02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Van02,
author = {Lan{-}Da Van},
title = {A new 2-D systolic digital filter architecture without global broadcast},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {477--486},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.800531},
doi = {10.1109/TVLSI.2002.800531},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Van02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCP02,
author = {Zhongfeng Wang and
Zhipei Chi and
Keshab K. Parhi},
title = {Area-efficient high-speed decoding schemes for turbo decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {6},
pages = {902--912},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.808451},
doi = {10.1109/TVLSI.2002.808451},
timestamp = {Thu, 15 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiZRCJ02,
author = {Liqiong Wei and
Rongtian Zhang and
Kaushik Roy and
Zhanping Chen and
David B. Janes},
title = {Vertically integrated {SOI} circuits for low-power and high-performance
applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {351--362},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043338},
doi = {10.1109/TVLSI.2002.1043338},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiZRCJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiuY02,
author = {Liming Xiu and
Zhihong You},
title = {A "flying-adder" architecture of frequency and phase synthesis with
scalability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {637--649},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801607},
doi = {10.1109/TVLSI.2002.801607},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiuY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Ykman-CouvreurLVCSHW02,
author = {Chantal Ykman{-}Couvreur and
Jurgen Lambrecht and
Diederik Verkest and
Francky Catthoor and
Bengt Svantesson and
Ahmed Hemani and
F. Wolf},
title = {Dynamic memory management methodology applied to embedded telecom
network systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {5},
pages = {650--667},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.801602},
doi = {10.1109/TVLSI.2002.801602},
timestamp = {Fri, 20 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Ykman-CouvreurLVCSHW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuG02,
author = {Jianwen Zhu and
Daniel D. Gajski},
title = {An ultra-fast instruction set simulator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {363--373},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043339},
doi = {10.1109/TVLSI.2002.1043339},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZiegenbeinRETT02,
author = {Dirk Ziegenbein and
Kai Richter and
Rolf Ernst and
Lothar Thiele and
J{\"{u}}rgen Teich},
title = {{SPI} - a system model for heterogeneously specified embedded systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {4},
pages = {379--389},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.807767},
doi = {10.1109/TVLSI.2002.807767},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZiegenbeinRETT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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