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@article{DBLP:journals/trets/BurovskiyGSL17, author = {Pavel Burovskiy and Paul Grigoras and Spencer J. Sherwin and Wayne Luk}, title = {Efficient Assembly for High-Order Unstructured {FEM} Meshes {(FPL} 2015)}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {12:1--12:22}, year = {2017}, url = {https://doi.org/10.1145/3024064}, doi = {10.1145/3024064}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/BurovskiyGSL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/CardosoS17, author = {Jo{\~{a}}o M. P. Cardoso and Cristina Silvano}, title = {Introduction to the Special Section on {FPL} 2015}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {10:1--10:2}, year = {2017}, url = {https://doi.org/10.1145/3041224}, doi = {10.1145/3041224}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/CardosoS17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ChuSK17, author = {Thiem Van Chu and Shimpei Sato and Kenji Kise}, title = {Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single {FPGA}}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {4}, pages = {27:1--27:27}, year = {2017}, url = {https://doi.org/10.1145/3151758}, doi = {10.1145/3151758}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/ChuSK17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/FabryT17, author = {Pieter Fabry and David Thomas}, title = {Efficient Reconfigurable Architecture for Pricing Exotic Options}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {4}, pages = {29:1--29:22}, year = {2017}, url = {https://doi.org/10.1145/3158228}, doi = {10.1145/3158228}, timestamp = {Fri, 30 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/FabryT17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/FraserLMFTJL17, author = {Nicholas J. Fraser and JunKyu Lee and Duncan J. M. Moss and Julian Faraone and Stephen Tridgell and Craig T. Jin and Philip Heng Wai Leong}, title = {{FPGA} Implementations of Kernel Normalised Least Mean Squares Processors}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {4}, pages = {26:1--26:20}, year = {2017}, url = {https://doi.org/10.1145/3106744}, doi = {10.1145/3106744}, timestamp = {Tue, 29 Dec 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/FraserLMFTJL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/GerleinMBC17, author = {Eduardo A. Gerlein and Thomas Martin McGinnity and Ammar Belatreche and Sonya A. Coleman}, title = {Network on Chip Architecture for Multi-Agent Systems in {FPGA}}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {4}, pages = {25:1--25:22}, year = {2017}, url = {https://doi.org/10.1145/3121112}, doi = {10.1145/3121112}, timestamp = {Sat, 05 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/GerleinMBC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/GuHO17, author = {Chongyan Gu and Neil Hanley and M{\'{a}}ire O'Neill}, title = {Improved Reliability of FPGA-Based {PUF} Identification Generator Design}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {20:1--20:23}, year = {2017}, url = {https://doi.org/10.1145/3053681}, doi = {10.1145/3053681}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/GuHO17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/KapreG17, author = {Nachiket Kapre and Jan Gray}, title = {Hoplite: {A} Deflection-Routed Directional Torus NoC for FPGAs}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {14:1--14:24}, year = {2017}, url = {https://doi.org/10.1145/3027486}, doi = {10.1145/3027486}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/KapreG17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/KimA17, author = {Jin Hee Kim and Jason Helge Anderson}, title = {Synthesizable Standard Cell {FPGA} Fabrics Targetable by the Verilog-to-Routing {CAD} Flow}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {11:1--11:23}, year = {2017}, url = {https://doi.org/10.1145/3024063}, doi = {10.1145/3024063}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/KimA17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/LaForestA17, author = {Charles Eric LaForest and Jason Helge Anderson}, title = {Microarchitectural Comparison of the {MXP} and Octavo Soft-Processor {FPGA} Overlays}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {19:1--19:25}, year = {2017}, url = {https://doi.org/10.1145/3053679}, doi = {10.1145/3053679}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/LaForestA17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/LeongAABCDGHLLL17, author = {Philip Heng Wai Leong and Hideharu Amano and Jason Helge Anderson and Koen Bertels and Jo{\~{a}}o M. P. Cardoso and Oliver Diessel and Guy Gogniat and Mike Hutton and JunKyu Lee and Wayne Luk and Patrick Lysaght and Marco Platzner and Viktor K. Prasanna and Tero Rissa and Cristina Silvano and Hayden Kwok{-}Hay So and Yu Wang}, title = {The First 25 Years of the {FPL} Conference: Significant Papers}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {15:1--15:17}, year = {2017}, url = {https://doi.org/10.1145/2996468}, doi = {10.1145/2996468}, timestamp = {Mon, 26 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/LeongAABCDGHLLL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/LiuDJXLZX17, author = {Zhiqiang Liu and Yong Dou and Jingfei Jiang and Jinwei Xu and Shijie Li and Yongmei Zhou and Yingnan Xu}, title = {Throughput-Optimized {FPGA} Accelerator for Deep Convolutional Neural Networks}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {17:1--17:23}, year = {2017}, url = {https://doi.org/10.1145/3079758}, doi = {10.1145/3079758}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/LiuDJXLZX17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/Prost-BouclePLA17, author = {Adrien Prost{-}Boucle and Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot and Vincent Leroy and Hande Alemdar}, title = {Efficient and Versatile {FPGA} Acceleration of Support Counting for Stream Mining of Sequences and Frequent Itemsets}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {21:1--21:25}, year = {2017}, url = {https://doi.org/10.1145/3027485}, doi = {10.1145/3027485}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/Prost-BouclePLA17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/RieblerLMLP17, author = {Heinrich Riebler and Michael Lass and Robert Mittendorf and Thomas L{\"{o}}cke and Christian Plessl}, title = {Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {24:1--24:23}, year = {2017}, url = {https://doi.org/10.1145/3053687}, doi = {10.1145/3053687}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/RieblerLMLP17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/Takano17, author = {Shigeyuki Takano}, title = {Performance Scalability of Adaptive Processor Architecture}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {16:1--16:22}, year = {2017}, url = {https://doi.org/10.1145/3007902}, doi = {10.1145/3007902}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/Takano17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/TiliOS17, author = {Ilian Tili and Kalin Ovtcharov and J. Gregory Steffan}, title = {Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware with {TILT}}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {22:1--22:23}, year = {2017}, url = {https://doi.org/10.1145/3079757}, doi = {10.1145/3079757}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/TiliOS17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/UenoSY17, author = {Tomohiro Ueno and Kentaro Sano and Satoru Yamamoto}, title = {Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {18:1--18:22}, year = {2017}, url = {https://doi.org/10.1145/3053688}, doi = {10.1145/3053688}, timestamp = {Sun, 12 Nov 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/UenoSY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/WulfGG17, author = {Nicholas Wulf and Alan D. George and Ann Gordon{-}Ross}, title = {Optimizing {FPGA} Performance, Power, and Dependability with Linear Programming}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {3}, pages = {23:1--23:23}, year = {2017}, url = {https://doi.org/10.1145/3079756}, doi = {10.1145/3079756}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/WulfGG17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/YangFWAE17, author = {Hsin{-}Jung Yang and Kermin Fleming and Felix Winterstein and Michael Adler and Joel S. Emer}, title = {{(FPL} 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {2}, pages = {13:1--13:23}, year = {2017}, url = {https://doi.org/10.1145/3009971}, doi = {10.1145/3009971}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/YangFWAE17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/YoshimiOY17, author = {Masato Yoshimi and Yasin Oge and Tsutomu Yoshinaga}, title = {Pipelined Parallel Join and Its FPGA-Based Acceleration}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {4}, pages = {28:1--28:28}, year = {2017}, url = {https://doi.org/10.1145/3079759}, doi = {10.1145/3079759}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/YoshimiOY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/BourgeMR16, author = {Alban Bourge and Olivier Muller and Fr{\'{e}}d{\'{e}}ric Rousseau}, title = {Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {9:1--9:23}, year = {2016}, url = {https://doi.org/10.1145/2996199}, doi = {10.1145/2996199}, timestamp = {Mon, 04 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/BourgeMR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ChaoTH16, author = {Hung{-}Lin Chao and Sheng{-}Ya Tung and Pao{-}Ann Hsiung}, title = {Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {3:1--3:25}, year = {2016}, url = {https://doi.org/10.1145/2892633}, doi = {10.1145/2892633}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/ChaoTH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/GalBRS16, author = {Bertrand Le Gal and Y{\'{e}}rom{-}David Bromberg and Laurent R{\'{e}}veill{\`{e}}re and Jigar Solanki}, title = {A Flexible SoC and Its Methodology for Parser-Based Applications}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {4:1--4:23}, year = {2016}, url = {https://doi.org/10.1145/2939379}, doi = {10.1145/2939379}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/GalBRS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/PangWPPFL16, author = {Yeyong Pang and Shaojun Wang and Yu Peng and Xiyuan Peng and Nicholas J. Fraser and Philip Heng Wai Leong}, title = {A Microcoded Kernel Recursive Least Squares Processor Using {FPGA} Technology}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {5:1--5:22}, year = {2016}, url = {https://doi.org/10.1145/2950061}, doi = {10.1145/2950061}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/PangWPPFL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/RichardsonGCL16, author = {Justin Richardson and Alan D. George and Kevin Cheng and Herman Lam}, title = {Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, {\&} Realizable-Utilization Metrics}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {2:1--2:21}, year = {2016}, url = {https://doi.org/10.1145/2888401}, doi = {10.1145/2888401}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/RichardsonGCL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/RouhaniMSK16, author = {Bita Darvish Rouhani and Azalia Mirhoseini and Ebrahim M. Songhori and Farinaz Koushanfar}, title = {Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {8:1--8:22}, year = {2016}, url = {https://doi.org/10.1145/2974023}, doi = {10.1145/2974023}, timestamp = {Fri, 04 Jun 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/RouhaniMSK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/TangK16, author = {Qing Y. Tang and Mohammed A. S. Khalid}, title = {Acceleration of k-Means Algorithm Using Altera {SDK} for OpenCL}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {6:1--6:19}, year = {2016}, url = {https://doi.org/10.1145/2964910}, doi = {10.1145/2964910}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/TangK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/WongBR16, author = {Henry Wong and Vaughn Betz and Jonathan Rose}, title = {Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {7:1--7:22}, year = {2016}, url = {https://doi.org/10.1145/2974022}, doi = {10.1145/2974022}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/WongBR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/WulfGG16, author = {Nicholas Wulf and Alan D. George and Ann Gordon{-}Ross}, title = {A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {10}, number = {1}, pages = {1:1--1:29}, year = {2016}, url = {https://doi.org/10.1145/2888400}, doi = {10.1145/2888400}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/WulfGG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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