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@article{DBLP:journals/todaes/0001GCBEP14,
  author       = {Reinhard Schneider and
                  Dip Goswami and
                  Samarjit Chakraborty and
                  Unmesh D. Bordoloi and
                  Petru Eles and
                  Zebo Peng},
  title        = {Quantifying Notions of Extensibility in FlexRay Schedule Synthesis},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {32:1--32:37},
  year         = {2014},
  url          = {https://doi.org/10.1145/2647954},
  doi          = {10.1145/2647954},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/0001GCBEP14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/BathenD14,
  author       = {Luis Angel D. Bathen and
                  Nikil D. Dutt},
  title        = {\emph{SPMCloud}: Towards the Single-Chip Embedded ScratchPad Memory-Based
                  Storage Cloud},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {22:1--22:45},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611755},
  doi          = {10.1145/2611755},
  timestamp    = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/BathenD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/BiswasWB14,
  author       = {Sounil Biswas and
                  Hongfei Wang and
                  R. D. (Shawn) Blanton},
  title        = {Reducing test cost of integrated, heterogeneous systems using pass-fail
                  test data analysis},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {20:1--20:23},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566666},
  doi          = {10.1145/2566666},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/BiswasWB14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/BoghratiS14,
  author       = {Baktash Boghrati and
                  Sachin S. Sapatnekar},
  title        = {Incremental Analysis of Power Grids Using Backward Random Walks},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {31:1--31:29},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611763},
  doi          = {10.1145/2611763},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/BoghratiS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ChangCYC14,
  author       = {Da{-}Wei Chang and
                  Hsin{-}Hung Chen and
                  Dau{-}Jieu Yang and
                  Hsung{-}Pin Chang},
  title        = {{BLAS:} Block-level adaptive striping for solid-state drives},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {21:1--21:29},
  year         = {2014},
  url          = {https://doi.org/10.1145/2555616},
  doi          = {10.1145/2555616},
  timestamp    = {Sat, 09 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/ChangCYC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ErbKSHSWB14,
  author       = {Dominik Erb and
                  Michael A. Kochte and
                  Matthias Sauer and
                  Stefan Hillebrecht and
                  Tobias Schubert and
                  Hans{-}Joachim Wunderlich and
                  Bernd Becker},
  title        = {Exact Logic and Fault Simulation in Presence of Unknowns},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {28:1--28:17},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611760},
  doi          = {10.1145/2611760},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/ErbKSHSWB14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/GaneshpureK14,
  author       = {Kunal P. Ganeshpure and
                  Sandip Kundu},
  title        = {Performance-driven dynamic thermal management of MPSoC based on task
                  rescheduling},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {11:1--11:33},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566661},
  doi          = {10.1145/2566661},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/GaneshpureK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/HatamiBPW14,
  author       = {Nadereh Hatami and
                  Rafal Baranowski and
                  Paolo Prinetto and
                  Hans{-}Joachim Wunderlich},
  title        = {Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {37:1--37:21},
  year         = {2014},
  url          = {https://doi.org/10.1145/2647955},
  doi          = {10.1145/2647955},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/HatamiBPW14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/HoHL14,
  author       = {Yenpo Ho and
                  Garng M. Huang and
                  Peng Li},
  title        = {Understanding {SRAM} Stability via Bifurcation Analysis: Analytical
                  Models and Scaling Trends},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {41:1--41:25},
  year         = {2014},
  url          = {https://doi.org/10.1145/2647957},
  doi          = {10.1145/2647957},
  timestamp    = {Thu, 31 Oct 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/HoHL14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/HuangCLWH14,
  author       = {Po{-}Chun Huang and
                  Yuan{-}Hao Chang and
                  Kam{-}yiu Lam and
                  Jiantao Wang and
                  Chien{-}Chin Huang},
  title        = {Garbage Collection for Multiversion Index in Flash-Based Embedded
                  Databases},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {25:1--25:27},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611757},
  doi          = {10.1145/2611757},
  timestamp    = {Tue, 05 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/HuangCLWH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/HuangWXWD14,
  author       = {Libo Huang and
                  Zhiying Wang and
                  Nong Xiao and
                  Yongwen Wang and
                  Qiang Dou},
  title        = {Integrated Coherence Prediction: Towards Efficient Cache Coherence
                  on NoC-Based Multicore Architectures},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {24:1--24:22},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611756},
  doi          = {10.1145/2611756},
  timestamp    = {Wed, 02 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/HuangWXWD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/HungW14,
  author       = {Eddie Hung and
                  Steven J. E. Wilton},
  title        = {Accelerating {FPGA} debug: Increasing visibility using a runtime reconfigurable
                  observation and triggering network},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {14:1--14:23},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566668},
  doi          = {10.1145/2566668},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/HungW14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/JoseM14,
  author       = {John Jose and
                  Madhu Mutyam},
  title        = {Implementation and Analysis of History-Based Output Channel Selection
                  Strategies for Adaptive Routers in Mesh NoCs},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {35:1--35:22},
  year         = {2014},
  url          = {https://doi.org/10.1145/2647952},
  doi          = {10.1145/2647952},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/JoseM14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/JuanGM14,
  author       = {Da{-}Cheng Juan and
                  Siddharth Garg and
                  Diana Marculescu},
  title        = {Statistical Peak Temperature Prediction and Thermal Yield Improvement
                  for 3D Chip Multiprocessors},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {39:1--39:23},
  year         = {2014},
  url          = {https://doi.org/10.1145/2633606},
  doi          = {10.1145/2633606},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/JuanGM14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/KangK14,
  author       = {Minseok Kang and
                  Taewhan Kim},
  title        = {Integrated Resource Allocation and Binding in Clock Mesh Synthesis},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {30:1--30:28},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611762},
  doi          = {10.1145/2611762},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/KangK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LeeC14,
  author       = {Seokhyun Lee and
                  Kiyoung Choi},
  title        = {Critical-path-aware high-level synthesis with distributed controller
                  for fast timing closure},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {16:1--16:29},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566670},
  doi          = {10.1145/2566670},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LeeC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LeeH14,
  author       = {Chia{-}Wei Lee and
                  Sun{-}Yuan Hsieh},
  title        = {Diagnosability of Component-Composition Graphs in the MM* Model},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {27:1--27:14},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611759},
  doi          = {10.1145/2611759},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LeeH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LeeSPC14,
  author       = {Jongeun Lee and
                  Seongseok Seo and
                  Jong Kyung Paek and
                  Kiyoung Choi},
  title        = {Configurable range memory for effective data reuse on programmable
                  accelerators},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {13:1--13:22},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566662},
  doi          = {10.1145/2566662},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LeeSPC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LimLKSYS14,
  author       = {Jieun Lim and
                  Nagesh B. Lakshminarayana and
                  Hyesoon Kim and
                  William J. Song and
                  Sudhakar Yalamanchili and
                  Wonyong Sung},
  title        = {Power Modeling for {GPU} Architectures Using McPAT},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {26:1--26:24},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611758},
  doi          = {10.1145/2611758},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/LimLKSYS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LivramentoGGJ14,
  author       = {Vinicius S. Livramento and
                  Chrystian Guth and
                  Jos{\'{e}} Lu{\'{\i}}s Almada G{\"{u}}ntzel and
                  Marcelo O. Johann},
  title        = {A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {40:1--40:25},
  year         = {2014},
  url          = {https://doi.org/10.1145/2647956},
  doi          = {10.1145/2647956},
  timestamp    = {Fri, 11 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/LivramentoGGJ14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/MeyerHT14,
  author       = {Brett H. Meyer and
                  Adam S. Hartman and
                  Donald E. Thomas},
  title        = {Cost-effective lifetime and yield optimization for NoC-based MPSoCs},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {12:1--12:33},
  year         = {2014},
  url          = {https://doi.org/10.1145/2535575},
  doi          = {10.1145/2535575},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/MeyerHT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/PanJL14,
  author       = {Gung{-}Yu Pan and
                  Jing{-}Yang Jou and
                  Bo{-}Cheng Lai},
  title        = {Scalable Power Management Using Multilevel Reinforcement Learning
                  for Multiprocessors},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {33:1--33:23},
  year         = {2014},
  url          = {https://doi.org/10.1145/2629486},
  doi          = {10.1145/2629486},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/PanJL14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/PaneratiB14,
  author       = {Jacopo Panerati and
                  Giovanni Beltrame},
  title        = {A comparative evaluation of multi-objective exploration algorithms
                  for high-level design},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {15:1--15:22},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566669},
  doi          = {10.1145/2566669},
  timestamp    = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/PaneratiB14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Pomeranz14,
  author       = {Irith Pomeranz},
  title        = {Low-power skewed-load tests based on functional broadside tests},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {18:1--18:18},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566664},
  doi          = {10.1145/2566664},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/Pomeranz14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Pomeranz14a,
  author       = {Irith Pomeranz},
  title        = {Design-for-testability for multi-cycle broadside tests by holding
                  of state variables},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {19:1--19:20},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566665},
  doi          = {10.1145/2566665},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/Pomeranz14a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/RaviJ14,
  author       = {Srivaths Ravi and
                  Michael Joseph},
  title        = {High-Level Test Synthesis: {A} Survey from Synthesis Process Flow
                  Perspective},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {38:1--38:27},
  year         = {2014},
  url          = {https://doi.org/10.1145/2627754},
  doi          = {10.1145/2627754},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/RaviJ14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/RosalesGT0XH14,
  author       = {Rafael Rosales and
                  Michael Gla{\ss} and
                  J{\"{u}}rgen Teich and
                  Bo Wang and
                  Yang Xu and
                  Ralph Hasholzner},
  title        = {{MAESTRO} - Holistic Actor-Oriented Modeling of Nonfunctional Properties
                  and Firmware Behavior for MPSoCs},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {23:1--23:26},
  year         = {2014},
  url          = {https://doi.org/10.1145/2594481},
  doi          = {10.1145/2594481},
  timestamp    = {Tue, 12 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/RosalesGT0XH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/TsaiCL14,
  author       = {Kun{-}Lin Tsai and
                  Hao{-}Tse Chen and
                  Yo{-}An Lin},
  title        = {Power and Area Efficiency NoC Router Design for Application-Specific
                  SoC by Using Buffer Merging and Resource Sharing},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {36:1--36:21},
  year         = {2014},
  url          = {https://doi.org/10.1145/2633604},
  doi          = {10.1145/2633604},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/TsaiCL14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/TuHCCH14,
  author       = {Chia{-}Heng Tu and
                  Hui{-}Hsin Hsu and
                  Jen{-}Hao Chen and
                  Chun{-}Han Chen and
                  Shih{-}Hao Hung},
  title        = {Performance and power profiling for emulated Android systems},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {10:1--10:25},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566660},
  doi          = {10.1145/2566660},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/TuHCCH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/WeiSVLARHTKS14,
  author       = {Yaoguang Wei and
                  Cliff C. N. Sze and
                  Natarajan Viswanathan and
                  Zhuo Li and
                  Charles J. Alpert and
                  Lakshmi N. Reddy and
                  Andrew D. Huber and
                  Gustavo E. T{\'{e}}llez and
                  Douglas Keller and
                  Sachin S. Sapatnekar},
  title        = {Techniques for scalable and effective routability evaluation},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {2},
  pages        = {17:1--17:37},
  year         = {2014},
  url          = {https://doi.org/10.1145/2566663},
  doi          = {10.1145/2566663},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/WeiSVLARHTKS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/YanVC14,
  author       = {Jackey Z. Yan and
                  Natarajan Viswanathan and
                  Chris Chu},
  title        = {An Effective Floorplan-Guided Placement Algorithm for Large-Scale
                  Mixed-Size Designs},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {3},
  pages        = {29:1--29:25},
  year         = {2014},
  url          = {https://doi.org/10.1145/2611761},
  doi          = {10.1145/2611761},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/YanVC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/YangKCG14,
  author       = {Yoon Seok Yang and
                  Reeshav Kumar and
                  Gwan S. Choi and
                  Paul V. Gratz},
  title        = {WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {4},
  pages        = {34:1--34:22},
  year         = {2014},
  url          = {https://doi.org/10.1145/2647950},
  doi          = {10.1145/2647950},
  timestamp    = {Tue, 29 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/YangKCG14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Al-DujailyDMXY13,
  author       = {Ra'ed Al{-}Dujaily and
                  Nizar Dahir and
                  Terrence S. T. Mak and
                  Fei Xia and
                  Alex Yakovlev},
  title        = {Dynamic programming-based runtime thermal management {(DPRTM):} An
                  online thermal control strategy for 3D-NoC systems},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {2:1--2:27},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534382},
  doi          = {10.1145/2534382},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/Al-DujailyDMXY13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/AyoubNR13,
  author       = {Raid Ayoub and
                  Rajib Nath and
                  Tajana Simunic Rosing},
  title        = {CoMETC: Coordinated management of energy/thermal/cooling in servers},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {1:1--1:28},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534381},
  doi          = {10.1145/2534381},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/AyoubNR13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ChangL13,
  author       = {Yen{-}Jen Chang and
                  Hsiang{-}Yu Lu},
  title        = {Improving the performance of port range check for network packet filtering},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {3:1--3:21},
  year         = {2013},
  url          = {https://doi.org/10.1145/2523069},
  doi          = {10.1145/2523069},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/ChangL13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/HuangWCL13,
  author       = {Chien{-}Chih Huang and
                  Chin{-}Long Wey and
                  Jwu{-}E Chen and
                  Pei{-}Wen Luo},
  title        = {Optimal common-centroid-based unit capacitor placements for yield
                  enhancement of switched-capacitor circuits},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {7:1--7:13},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534394},
  doi          = {10.1145/2534394},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/HuangWCL13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/KritikakouCKG13,
  author       = {Angeliki Kritikakou and
                  Francky Catthoor and
                  Vasilios I. Kelefouras and
                  Costas E. Goutis},
  title        = {Near-optimal and scalable intrasignal in-place optimization for non-overlapping
                  and irregular access schemes},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {4:1--4:30},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534383},
  doi          = {10.1145/2534383},
  timestamp    = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/KritikakouCKG13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LiSLXCXW13,
  author       = {Jianhua Li and
                  Liang Shi and
                  Qing'an Li and
                  Chun Jason Xue and
                  Yiran Chen and
                  Yinlong Xu and
                  Wei Wang},
  title        = {Low-energy volatile {STT-RAM} cache design using cache-coherence-enabled
                  adaptive refresh},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {5:1--5:23},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534393},
  doi          = {10.1145/2534393},
  timestamp    = {Tue, 14 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LiSLXCXW13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LiuTPTS13,
  author       = {Xuexin Liu and
                  Sheldon X.{-}D. Tan and
                  Adolfo Adair Palma{-}Rodriguez and
                  Esteban Tlelo{-}Cuautle and
                  Guoyong Shi},
  title        = {Performance bound analysis of analog circuits in frequency- and time-domain
                  considering process variations},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {6:1--6:22},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534395},
  doi          = {10.1145/2534395},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LiuTPTS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Pomeranz13,
  author       = {Irith Pomeranz},
  title        = {Built-in generation of multicycle functional broadside tests with
                  observation points},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {8:1--8:17},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534396},
  doi          = {10.1145/2534396},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/Pomeranz13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/TongBZ13,
  author       = {Jason G. Tong and
                  Marc Boule and
                  Zeljko Zilic},
  title        = {Test compaction techniques for assertion-based test generation},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {19},
  number       = {1},
  pages        = {9:1--9:29},
  year         = {2013},
  url          = {https://doi.org/10.1145/2534397},
  doi          = {10.1145/2534397},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/TongBZ13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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