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@article{DBLP:journals/thipeac/AnsariLKJKW11, author = {Mohammad Ansari and Mikel Luj{\'{a}}n and Christos Kotselidis and Kim Jarvis and Chris C. Kirkham and Ian Watson}, title = {Robust Adaptation to Available Parallelism in Transactional Memory Applications}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {236--255}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_13}, doi = {10.1007/978-3-642-19448-1\_13}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/AnsariLKJKW11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/BartoliniFP11, author = {Sandro Bartolini and Pierfrancesco Foglia and Cosimo Antonio Prete}, title = {Eighth {MEDEA} Workshop}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {91--92}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_5}, doi = {10.1007/978-3-642-19448-1\_5}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/BartoliniFP11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/BlumrichSG11, author = {Matthias A. Blumrich and Valentina Salapura and Alan Gara}, title = {Exploring the Architecture of a Stream Register-Based Snoop Filter}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {93--114}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_6}, doi = {10.1007/978-3-642-19448-1\_6}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/BlumrichSG11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/DevosCVS11, author = {Harald Devos and Jan Van Campenhout and Ingrid Verbauwhede and Dirk Stroobandt}, title = {Constructing Application-Specific Memory Hierarchies on FPGAs}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {201--216}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_11}, doi = {10.1007/978-3-642-19448-1\_11}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/DevosCVS11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/GoudarziIN11, author = {Maziar Goudarzi and Tohru Ishihara and Hamid Noori}, title = {Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of {SRAM} Leakage in Nanometer Technologies}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {275--299}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_15}, doi = {10.1007/978-3-642-19448-1\_15}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/GoudarziIN11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/HoogerbruggeT11, author = {Jan Hoogerbrugge and Andrei Sergeevich Terechko}, title = {A Multithreaded Multicore System for Embedded Media Processing}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {154--173}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_9}, doi = {10.1007/978-3-642-19448-1\_9}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/HoogerbruggeT11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/KlugOWT11, author = {Tobias Klug and Michael Ott and Josef Weidendorfer and Carsten Trinitis}, title = {autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {219--235}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_12}, doi = {10.1007/978-3-642-19448-1\_12}, timestamp = {Wed, 07 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/KlugOWT11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/KoteraAETK11, author = {Isao Kotera and Kenta Abe and Ryusuke Egawa and Hiroyuki Takizawa and Hiroaki Kobayashi}, title = {Power-Aware Dynamic Cache Partitioning for CMPs}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {135--153}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_8}, doi = {10.1007/978-3-642-19448-1\_8}, timestamp = {Mon, 26 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/KoteraAETK11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/LatorreMGCG11, author = {Fernando Latorre and Grigorios Magklis and Jos{\'{e}} Gonz{\'{a}}lez and Pedro Chaparro and Antonio Gonz{\'{a}}lez}, title = {{CROB:} Implementing a Large Instruction Window through Compression}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {115--134}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_7}, doi = {10.1007/978-3-642-19448-1\_7}, timestamp = {Sat, 29 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/LatorreMGCG11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/LinC11, author = {Chun{-}Chieh Lin and Chuen{-}Liang Chen}, title = {Cache Sensitive Code Arrangement for Virtual Machine}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {24--42}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_2}, doi = {10.1007/978-3-642-19448-1\_2}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/LinC11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/MoretoCRV11, author = {Miquel Moret{\'{o}} and Francisco J. Cazorla and Alex Ram{\'{\i}}rez and Mateo Valero}, title = {Dynamic Cache Partitioning Based on the {MLP} of Cache Misses}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {3--23}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_1}, doi = {10.1007/978-3-642-19448-1\_1}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/MoretoCRV11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/SaidaniLFTB11, author = {Tarik Saidani and Lionel Lacassagne and Joel Falcou and Claude Tadonki and Samir Bouaziz}, title = {Parallelization Schemes for Memory Optimization on the Cell Processor: {A} Case Study on the Harris Corner Detector}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {177--200}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_10}, doi = {10.1007/978-3-642-19448-1\_10}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/SaidaniLFTB11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/SarkarT11, author = {Subhradyuti Sarkar and Dean M. Tullsen}, title = {Data Layout for Cache Performance on a Multithreaded Architecture}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {43--68}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_3}, doi = {10.1007/978-3-642-19448-1\_3}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/SarkarT11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/SazeidesMCK11, author = {Yiannakis Sazeides and Andreas Moustakas and Kypros Constantinides and Marios Kleanthous}, title = {Improving Branch Prediction by Considering Affectors and Affectees Correlations}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {69--88}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_4}, doi = {10.1007/978-3-642-19448-1\_4}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/SazeidesMCK11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/thipeac/Waliullah11, author = {M. M. Waliullah}, title = {Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems}, journal = {Trans. High Perform. Embed. Archit. Compil.}, volume = {3}, pages = {256--274}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1\_14}, doi = {10.1007/978-3-642-19448-1\_14}, timestamp = {Mon, 18 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/Waliullah11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:journals/thipeac/2011-3, editor = {Per Stenstr{\"{o}}m}, title = {Transactions on High-Performance Embedded Architectures and Compilers {III}}, series = {Lecture Notes in Computer Science}, volume = {6590}, publisher = {Springer}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-19448-1}, doi = {10.1007/978-3-642-19448-1}, isbn = {978-3-642-19447-4}, timestamp = {Tue, 14 May 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/thipeac/2011-3.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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