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@article{DBLP:journals/tcad/0001L0019,
author = {Ying Wang and
Huawei Li and
Long Cheng and
Xiaowei Li},
title = {A QoS-QoR Aware {CNN} Accelerator Design Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {1995--2007},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2877010},
doi = {10.1109/TCAD.2018.2877010},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/0001L0019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/0003ZYL19,
author = {Yi Wang and
Mingxu Zhang and
Xuan Yang and
Tao Li},
title = {A Thermal-Aware Physical Space Reallocation for Open-Channel {SSD}
With 3-D Flash Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {617--627},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2821442},
doi = {10.1109/TCAD.2018.2821442},
timestamp = {Wed, 15 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/0003ZYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AbdomerovicR19,
author = {Iskren Abdomerovic and
Sanjay Raman},
title = {A Millimeter Wave Loss-Aware Methodology for Switchless {PALNA} Integrated
Circuit Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2177--2190},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878189},
doi = {10.1109/TCAD.2018.2878189},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AbdomerovicR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AboutalebiAMWD19,
author = {Armin Haj Aboutalebi and
Ethan C. Ahn and
Bo Mao and
Suzhen Wu and
Lide Duan},
title = {Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main
Memory via Device and Architecture Innovations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2229--2242},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878166},
doi = {10.1109/TCAD.2018.2878166},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AboutalebiAMWD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AinD19,
author = {Antara Ain and
Pallab Dasgupta},
title = {Interpreting Local Variables in {AMS} Assertions During Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {980--984},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2824288},
doi = {10.1109/TCAD.2018.2824288},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AinD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlizadehS19,
author = {Bijan Alizadeh and
Seyyed Reza Sharafinejad},
title = {Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits
Through Automatic Test Pattern Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {245--252},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812123},
doi = {10.1109/TCAD.2018.2812123},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlizadehS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BecklerB19,
author = {Matthew Layne Beckler and
Ronald D. Blanton},
title = {On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault
Dictionaries},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {322--334},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2803621},
doi = {10.1109/TCAD.2018.2803621},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BecklerB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhattacharjeeBH19,
author = {Sukanta Bhattacharjee and
Ansuman Banerjee and
Tsung{-}Yi Ho and
Krishnendu Chakrabarty and
Bhargab B. Bhattacharya},
title = {Efficient Generation of Dilution Gradients With Digital Microfluidic
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {874--887},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834413},
doi = {10.1109/TCAD.2018.2834413},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhattacharjeeBH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BriskCCGGJ19,
author = {Philip Brisk and
Suman Chakraborty and
Claudionor Coelho and
Abdoulaye Gamati{\'{e}} and
Swaroop Ghosh and
Xun Jiao},
title = {{TCAD} {EIC} Message: February 2019},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {197--198},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2890315},
doi = {10.1109/TCAD.2018.2890315},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BriskCCGGJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CabodiCPPV19,
author = {Gianpiero Cabodi and
Paolo Camurati and
Marco Palena and
Paolo Pasini and
Danilo Vendraminetto},
title = {Logic Synthesis for Interpolant Circuit Compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {380--384},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808229},
doi = {10.1109/TCAD.2018.2808229},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CabodiCPPV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CampbellLC19,
author = {Keith A. Campbell and
Chen{-}Hsuan Lin and
Deming Chen},
title = {Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1056--1069},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834417},
doi = {10.1109/TCAD.2018.2834417},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CampbellLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CampbellLHYGRMC19,
author = {Keith A. Campbell and
David Lin and
Leon He and
Liwei Yang and
Swathi T. Gurumani and
Kyle Rupnow and
Subhasish Mitra and
Deming Chen},
title = {Hybrid Quick Error Detection: Validation and Debug of SoCs Through
High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1345--1358},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2837103},
doi = {10.1109/TCAD.2018.2837103},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CampbellLHYGRMC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoXLZLW19,
author = {Xuebing Cao and
Liyi Xiao and
Jie Li and
Rongsheng Zhang and
Shanshan Liu and
Jinxiang Wang},
title = {A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational
Circuits Considering Single Event Multiple Transients (SEMTs)},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1109--1122},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834425},
doi = {10.1109/TCAD.2018.2834425},
timestamp = {Wed, 10 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CaoXLZLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoXZWCH19,
author = {Kun Cao and
Guo Xu and
Junlong Zhou and
Tongquan Wei and
Mingsong Chen and
Shiyan Hu},
title = {QoS-Adaptive Approximate Real-Time Computation for Mobility-Aware
IoT Lifetime Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1799--1810},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2873239},
doi = {10.1109/TCAD.2018.2873239},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CaoXZWCH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoZCLWCHH19,
author = {Kun Cao and
Junlong Zhou and
Peijin Cong and
Liying Li and
Tongquan Wei and
Mingsong Chen and
Shiyan Hu and
Xiaobo Sharon Hu},
title = {Affinity-Driven Modeling and Scheduling for Makespan Optimization
in Heterogeneous Multiprocessor Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1189--1202},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846650},
doi = {10.1109/TCAD.2018.2846650},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CaoZCLWCHH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChanAAR19,
author = {Christine S. Chan and
Alper Sinan Aky{\"{u}}rek and
Baris Aksanli and
Tajana Simunic Rosing},
title = {Optimal Performance-Aware Cooling on Enterprise Servers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1689--1702},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855122},
doi = {10.1109/TCAD.2018.2855122},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChanAAR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangLLH19,
author = {Da{-}Wei Chang and
Ing{-}Chao Lin and
Yi{-}Chiao Lin and
Wen{-}Zhi Huang},
title = {{OCMAS:} Online Page Clustering for Multibank Scratchpad Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {220--233},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808228},
doi = {10.1109/TCAD.2018.2808228},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangLLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCH19,
author = {Wei{-}Ming Chen and
Sheng{-}Wei Cheng and
Pi{-}Cheng Hsiu},
title = {A User-Centric {CPU-GPU} Governing Framework for 3-D Mobile Games},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {961--974},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834404},
doi = {10.1109/TCAD.2018.2834404},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenXY19,
author = {Song Chen and
Qi Xu and
Bei Yu},
title = {Adaptive 3D-IC {TSV} Fault Tolerance Structure Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {949--960},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2824284},
doi = {10.1109/TCAD.2018.2824284},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenXY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenYCCWS19,
author = {Yen{-}Ting Chen and
Ming{-}Chang Yang and
Yuan{-}Hao Chang and
Tseng{-}Yi Chen and
Hsin{-}Wen Wei and
Wei{-}Kuan Shih},
title = {Co-Optimizing Storage Space Utilization and Performance for Key-Value
Solid State Drives},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {29--42},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801244},
doi = {10.1109/TCAD.2018.2801244},
timestamp = {Tue, 05 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenYCCWS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenZWSLSG19,
author = {Renhai Chen and
Chi Zhang and
Yi Wang and
Zhaoyan Shen and
Duo Liu and
Zili Shao and
Yong Guan},
title = {{DCR:} Deterministic Crash Recovery for {NAND} Flash Storage Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2201--2214},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878179},
doi = {10.1109/TCAD.2018.2878179},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenZWSLSG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengKKW19,
author = {Chung{-}Kuan Cheng and
Andrew B. Kahng and
Ilgweon Kang and
Lutong Wang},
title = {RePlAce: Advancing Solution Quality and Routability Validation in
Global Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1717--1730},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859220},
doi = {10.1109/TCAD.2018.2859220},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengKKW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengL0019,
author = {Yun Cheng and
Huawei Li and
Ying Wang and
Xiaowei Li},
title = {Cluster Restoration-Based Trace Signal Selection for Post-Silicon
Debug},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {767--779},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818690},
doi = {10.1109/TCAD.2018.2818690},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengL0019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengWZHB19,
author = {Huimei Cheng and
Hsiao{-}Lun Wang and
Minghe Zhang and
Dylan Hand and
Peter A. Beerel},
title = {Automatic Retiming of Two-Phase Latch-Based Resilient Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1305--1316},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846631},
doi = {10.1109/TCAD.2018.2846631},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengWZHB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengXZCXWY19,
author = {Ming Cheng and
Lixue Xia and
Zhenhua Zhu and
Yi Cai and
Yuan Xie and
Yu Wang and
Huazhong Yang},
title = {{TIME:} {A} Training-in-Memory Architecture for RRAM-Based Deep Neural
Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {834--847},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2824304},
doi = {10.1109/TCAD.2018.2824304},
timestamp = {Fri, 13 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengXZCXWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoHJA19,
author = {Jaeyong Cho and
Karam Hwang and
Seungil Jeung and
Seungyoung Ahn},
title = {An Efficient Extrapolation Method of Band-Limited S-Parameters for
Extracting Causal Impulse Responses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2086--2098},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878192},
doi = {10.1109/TCAD.2018.2878192},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoHJA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoLSK19,
author = {Keewon Cho and
Young{-}Woo Lee and
Sungyoul Seo and
Sungho Kang},
title = {An Efficient {BIRA} Utilizing Characteristics of Spare Pivot Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {551--561},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818725},
doi = {10.1109/TCAD.2018.2818725},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChoLSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiSS19,
author = {Suhyeong Choi and
Seongbo Shim and
Youngsoo Shin},
title = {Neural Network Classifier-Based {OPC} With Imbalanced Training Data},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {938--948},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2824255},
doi = {10.1109/TCAD.2018.2824255},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoukseyKB19,
author = {Ramanuj Chouksey and
Chandan Karfa and
Purandar Bhaduri},
title = {Translation Validation of Code Motion Transformations Involving Loops},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1378--1382},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846654},
doi = {10.1109/TCAD.2018.2846654},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoukseyKB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungSY19,
author = {Jaeyong Chung and
Taehwan Shin and
Joon{-}Sung Yang},
title = {Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2032--2042},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2877016},
doi = {10.1109/TCAD.2018.2877016},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungSY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaiB19,
author = {Yu{-}Yun Dai and
Robert K. Brayton},
title = {Verification and Synthesis of Clock-Gated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {366--379},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808231},
doi = {10.1109/TCAD.2018.2808231},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaiB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaiHCZSL00Y19,
author = {Guohao Dai and
Tianhao Huang and
Yuze Chi and
Jishen Zhao and
Guangyu Sun and
Yongpan Liu and
Yu Wang and
Yuan Xie and
Huazhong Yang},
title = {GraphH: {A} Processing-in-Memory Architecture for Large-Scale Graph
Processing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {640--653},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2821565},
doi = {10.1109/TCAD.2018.2821565},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaiHCZSL00Y19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasMRCB19,
author = {Satyajit Das and
Kevin J. M. Martin and
Davide Rossi and
Philippe Coussy and
Luca Benini},
title = {An Energy-Efficient Integrated Programmable Array Accelerator and
Compilation Flow for Near-Sensor Ultralow Power Processing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1095--1108},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834397},
doi = {10.1109/TCAD.2018.2834397},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasMRCB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuDGDWHJCIC19,
author = {Yuan Du and
Li Du and
Xuefeng Gu and
Jieqiong Du and
X. Shawn Wang and
Boyu Hu and
Mingzhe Jiang and
Xiaoliang Chen and
Subramanian S. Iyer and
Mau{-}Chung Frank Chang},
title = {An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor
{(CTT)}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1811--1819},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859237},
doi = {10.1109/TCAD.2018.2859237},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuDGDWHJCIC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuongYWCXWC19,
author = {Luan H. K. Duong and
Peng Yang and
Zhifei Wang and
Yi{-}Shing Chang and
Jiang Xu and
Zhehui Wang and
Xuanqi Chen},
title = {Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip
Optical Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {43--56},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801230},
doi = {10.1109/TCAD.2018.2801230},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DuongYWCXWC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EfendiogluSK19,
author = {Mustafa Efendioglu and
Alper Sen and
Yavuz K{\"{o}}roglu},
title = {Bug Prediction of SystemC Models Using Machine Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {419--429},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878193},
doi = {10.1109/TCAD.2018.2878193},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EfendiogluSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EwetzK19,
author = {Rickard Ewetz and
Cheng{-}Kok Koh},
title = {Scalable Construction of Clock Trees With Useful Skew and High Timing
Quality},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1161--1174},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834437},
doi = {10.1109/TCAD.2018.2834437},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EwetzK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeldS19,
author = {Timo Feld and
Frank Slomka},
title = {A Sufficient Response Time Analysis Considering Angular Phases Between
Rate-Dependent Tasks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2008--2021},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878163},
doi = {10.1109/TCAD.2018.2878163},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FeldS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FuLPWFCZ19,
author = {Yuxiang Fu and
Li Li and
Hongbing Pan and
Kun Wang and
Fan Feng and
Qinyu Chen and
Chuan Zhang},
title = {Thermal Sensor Placement and Thermal Reconstruction Under Gaussian
and Non-Gaussian Sensor Noises for 3-D NoC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2139--2152},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878178},
doi = {10.1109/TCAD.2018.2878178},
timestamp = {Fri, 26 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FuLPWFCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GebregiorgisBT19,
author = {Anteneh Gebregiorgis and
Rajendra Bishnoi and
Mehdi Baradaran Tahoori},
title = {A Comprehensive Reliability Analysis Framework for {NTC} Caches: {A}
System to Device Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {439--452},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818691},
doi = {10.1109/TCAD.2018.2818691},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GebregiorgisBT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrimmerHW19,
author = {Andreas Grimmer and
Werner Haselmayr and
Robert Wille},
title = {Automated Dimensioning of Networked Labs-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1216--1225},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834402},
doi = {10.1109/TCAD.2018.2834402},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrimmerHW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Guerra-PulidoP19,
author = {Jaime Octavio Guerra{-}Pulido and
Pablo Roberto P{\'{e}}rez{-}Alc{\'{a}}zar},
title = {Time-Domain Numerical Simulation of Electronic Circuits and Surface
Acoustic Wave Devices Using Their Admittance Parameters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {499--511},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818732},
doi = {10.1109/TCAD.2018.2818732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Guerra-PulidoP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaKR19,
author = {Utkarsh Gupta and
Priyank Kalla and
Vikas Rao},
title = {Boolean Gr{\"{o}}bner Basis Reductions on Finite Field Datapath
Circuits Using the Unate Cube Set Algebra},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {576--588},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818726},
doi = {10.1109/TCAD.2018.2818726},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Hadjitheophanous19,
author = {Stavros Hadjitheophanous and
Stelios N. Neophytou and
Maria K. Michael},
title = {Exploiting Shared-Memory to Steer Scalability of Fault Simulation
Using Multicore Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1466--1479},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855131},
doi = {10.1109/TCAD.2018.2855131},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Hadjitheophanous19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanKWX19,
author = {Changho Han and
Andrew B. Kahng and
Lutong Wang and
Bangqi Xu},
title = {Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion
Effect Mitigation in Sub-10 nm {VLSI}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1703--1716},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859266},
doi = {10.1109/TCAD.2018.2859266},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanKWX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HarutyunyanSZ19,
author = {Gurgen Harutyunyan and
Samvel K. Shoukourian and
Yervant Zorian},
title = {Fault Awareness for Memory {BIST} Architecture Shaped by Multidimensional
Prediction Mechanism},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {562--575},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818688},
doi = {10.1109/TCAD.2018.2818688},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HarutyunyanSZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HerdtLGD19,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Verifying SystemC Using Intermediate Verification Language and Stateful
Symbolic Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1359--1372},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846638},
doi = {10.1109/TCAD.2018.2846638},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HerdtLGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HongKHC19,
author = {JuHyung Hong and
Jeongbin Kim and
Sangwoo Han and
Eui{-}Young Chung},
title = {A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {453--465},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818692},
doi = {10.1109/TCAD.2018.2818692},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HongKHC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HongLWZ19,
author = {Qinghui Hong and
Ya Li and
Xiaoping Wang and
Zhigang Zeng},
title = {A Versatile Pulse Control Method to Generate Arbitrary Multidirection
Multibutterfly Chaotic Attractors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1480--1492},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855121},
doi = {10.1109/TCAD.2018.2855121},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HongLWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HouHSJWW19,
author = {Yumin Hou and
Hu He and
Kaveh Shamsi and
Yier Jin and
Dong Wu and
Huaqiang Wu},
title = {On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1820--1830},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864246},
doi = {10.1109/TCAD.2018.2864246},
timestamp = {Wed, 12 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HouHSJWW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehWSHPCL19,
author = {Shih{-}An Hsieh and
Ying{-}Hsu Wang and
Ting{-}Yu Shen and
Kuan{-}Yen Huang and
Chia{-}Cheng Pai and
Tsai{-}Chieh Chen and
James Chien{-}Mo Li},
title = {DR-Scan: Dual-Rail Asynchronous Scan DfT and {ATPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {136--148},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801226},
doi = {10.1109/TCAD.2018.2801226},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehWSHPCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLHCYW19,
author = {Hai Huang and
Leibo Liu and
Qihuan Huang and
Yingjie Chen and
Shouyi Yin and
Shaojun Wei},
title = {Low Area-Overhead Low-Entropy Masking Scheme {(LEMS)} Against Correlation
Power Analysis Attack},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {208--219},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2802867},
doi = {10.1109/TCAD.2018.2802867},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLHCYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLW19,
author = {Tsung{-}Wei Huang and
Chun{-}Xun Lin and
Martin D. F. Wong},
title = {DtCraft: {A} High-Performance Distributed Execution Engine at Scale},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1070--1083},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834422},
doi = {10.1109/TCAD.2018.2834422},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangM19,
author = {Yuanwen Huang and
Prabhat Mishra},
title = {Vulnerability-Aware Energy Optimization for Reconfigurable Caches
in Multitasking Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {809--821},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834410},
doi = {10.1109/TCAD.2018.2834410},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangZZYJYBJ19,
author = {Kai Huang and
Xiaomeng Zhang and
Dan{-}dan Zheng and
Min Yu and
Xiaowen Jiang and
Xiaolang Yan and
Lisane B. de Brisolara and
Ahmed Amine Jerraya},
title = {A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC
Considering Load Balance and Communication Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1744--1757},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859400},
doi = {10.1109/TCAD.2018.2859400},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuangZZYJYBJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IbrahimCS19,
author = {Mohamed Ibrahim and
Krishnendu Chakrabarty and
Ulf Schlichtmann},
title = {Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1237--1250},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846662},
doi = {10.1109/TCAD.2018.2846662},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IbrahimCS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IbrahimSCS19,
author = {Mohamed Ibrahim and
Aditya Sridhar and
Krishnendu Chakrabarty and
Ulf Schlichtmann},
title = {Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell
Screening},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2255--2270},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878159},
doi = {10.1109/TCAD.2018.2878159},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IbrahimSCS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ImaniGSR19,
author = {Mohsen Imani and
Saransh Gupta and
Sahil Sharma and
Tajana Simunic Rosing},
title = {NVQuery: Efficient Query Processing in Nonvolatile Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {628--639},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2819080},
doi = {10.1109/TCAD.2018.2819080},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ImaniGSR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JangCK19,
author = {Jaewon Jang and
Minho Cheong and
Sungho Kang},
title = {{TSV} Repair Architecture for Clustered Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {190--194},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808453},
doi = {10.1109/TCAD.2018.2808453},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JangCK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangPJWD19,
author = {Wei Jiang and
Xiong Pan and
Ke Jiang and
Liang Wen and
Qi Dong},
title = {Energy-Aware Design of Stochastic Applications With Statistical Deadline
and Reliability Guarantees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1413--1426},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846652},
doi = {10.1109/TCAD.2018.2846652},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangPJWD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangSZYCH19,
author = {Weiwen Jiang and
Edwin Hsing{-}Mean Sha and
Qingfeng Zhuge and
Lei Yang and
Xianzhang Chen and
Jingtong Hu},
title = {On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1515--1528},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846642},
doi = {10.1109/TCAD.2018.2846642},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangSZYCH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JinZCG19,
author = {Shi Jin and
Zhaobo Zhang and
Krishnendu Chakrabarty and
Xinli Gu},
title = {Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a
Core Router System},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1331--1344},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846641},
doi = {10.1109/TCAD.2018.2846641},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JinZCG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KampmannK0SHW19,
author = {Matthias Kampmann and
Michael A. Kochte and
Chang Liu and
Eric Schneider and
Sybille Hellebrand and
Hans{-}Joachim Wunderlich},
title = {Built-In Test for Hidden Delay Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1956--1968},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864255},
doi = {10.1109/TCAD.2018.2864255},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KampmannK0SHW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KangYC19,
author = {Yongshin Kang and
Joon{-}Sung Yang and
Jaeyong Chung},
title = {Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2167--2171},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878167},
doi = {10.1109/TCAD.2018.2878167},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KangYC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Kasprowicz19,
author = {Dominik Kasprowicz},
title = {Table-Based Model of a Dual-Gate Transistor for Statistical Circuit
Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1493--1500},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2852756},
doi = {10.1109/TCAD.2018.2852756},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Kasprowicz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KoKNM19,
author = {Jong Hwan Ko and
Duckhwan Kim and
Taesik Na and
Saibal Mukhopadhyay},
title = {Design and Analysis of a Neural Network Inference Engine Based on
Adaptive Weight Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {109--121},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801228},
doi = {10.1109/TCAD.2018.2801228},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KoKNM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KoneruKC19,
author = {Abhishek Koneru and
Sukeshwar Kannan and
Krishnendu Chakrabarty},
title = {A Design-for-Test Solution Based on Dedicated Test Layers and Test
Scheduling for Monolithic 3-D Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1942--1955},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864290},
doi = {10.1109/TCAD.2018.2864290},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KoneruKC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuangY19,
author = {Jian Kuang and
Evangeline F. Y. Young},
title = {Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition
and Beyond},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1731--1743},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859255},
doi = {10.1109/TCAD.2018.2859255},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuangY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LahtiSVH19,
author = {Sakari Lahti and
Panu Sjovall and
Jarno Vanne and
Timo D. H{\"{a}}m{\"{a}}l{\"{a}}inen},
title = {Are We There Yet? {A} Study on the State of High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {898--911},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834439},
doi = {10.1109/TCAD.2018.2834439},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LahtiSVH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCK19,
author = {Kuen{-}Jong Lee and
Bo{-}Ren Chen and
Michael Andreas Kochte},
title = {On-Chip Self-Test Methodology With All Deterministic Compressed Test
Patterns Recorded in Scan Chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {309--321},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808241},
doi = {10.1109/TCAD.2018.2808241},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKLHKP19,
author = {Woojoo Lee and
Taewook Kang and
Jae{-}Jin Lee and
Kyuseung Han and
Joongheon Kim and
Massoud Pedram},
title = {{TEI-ULP:} Exploiting Body Biasing to Improve the TEI-Aware Ultralow
Power Methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1758--1770},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859240},
doi = {10.1109/TCAD.2018.2859240},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKLHKP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKNL19,
author = {Sugil Lee and
Daewoo Kim and
Dong Nguyen and
Jongeun Lee},
title = {Double {MAC} on a {DSP:} Boosting the Performance of Convolutional
Neural Networks on FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {888--897},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2824280},
doi = {10.1109/TCAD.2018.2824280},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKNL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LewisS19,
author = {David M. Lewis and
Herman Schmit},
title = {Spatial Timing Analysis With Exact Propagation of Delay and Application
to {FPGA} Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2153--2166},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878170},
doi = {10.1109/TCAD.2018.2878170},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LewisS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiCCZWCHH19,
author = {Liying Li and
Peijin Cong and
Kun Cao and
Junlong Zhou and
Tongquan Wei and
Mingsong Chen and
Shiyan Hu and
Xiaobo Sharon Hu},
title = {Game Theoretic Feedback Control for Reliability Enhancement of EtherCAT-Based
Networked Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1599--1610},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859241},
doi = {10.1109/TCAD.2018.2859241},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiCCZWCHH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiCZHQ19,
author = {Zhijing Li and
Zhao Chen and
Yili Zhang and
Zixin Huang and
Weikang Qian},
title = {Simultaneous Area and Latency Optimization for Stochastic Circuits
by {D} Flip-Flop Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1251--1264},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846660},
doi = {10.1109/TCAD.2018.2846660},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiCZHQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLRCDQDYTQW19,
author = {Zhe Li and
Ji Li and
Ao Ren and
Ruizhe Cai and
Caiwen Ding and
Xuehai Qian and
Jeffrey Draper and
Bo Yuan and
Jian Tang and
Qinru Qiu and
Yanzhi Wang},
title = {{HEIF:} Highly Efficient Stochastic Computing-Based Inference Framework
for Deep Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1543--1556},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2852752},
doi = {10.1109/TCAD.2018.2852752},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLRCDQDYTQW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiP19,
author = {Wuxi Li and
David Z. Pan},
title = {A New Paradigm for {FPGA} Placement Without Explicit Packing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2113--2126},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2877017},
doi = {10.1109/TCAD.2018.2877017},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiQZHLGX19,
author = {Fuyang Li and
Keni Qiu and
Mengying Zhao and
Jingtong Hu and
Yongpan Liu and
Yong Guan and
Chun Jason Xue},
title = {Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile
Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {15--28},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2803624},
doi = {10.1109/TCAD.2018.2803624},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiQZHLGX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiSMZYJP19,
author = {Meng Li and
Kaveh Shamsi and
Travis Meade and
Zheng Zhao and
Bei Yu and
Yier Jin and
David Z. Pan},
title = {Provably Secure Camouflaging Strategy for {IC} Protection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1399--1412},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2017.2750088},
doi = {10.1109/TCAD.2017.2750088},
timestamp = {Fri, 30 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiSMZYJP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiYLXLP19,
author = {Meng Li and
Bei Yu and
Yibo Lin and
Xiaoqing Xu and
Wuxi Li and
David Z. Pan},
title = {A Practical Split Manufacturing Framework for Trojan Prevention via
Simultaneous Wire Lifting and Cell Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1585--1598},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859402},
doi = {10.1109/TCAD.2018.2859402},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiYLXLP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiZZ19,
author = {Yaguang Li and
Cheng Zhuo and
Pingqiang Zhou},
title = {A Cross-Layer Framework for Temporal Power and Supply Noise Prediction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1914--1927},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2871820},
doi = {10.1109/TCAD.2018.2871820},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Lin0WKMNP19,
author = {Yibo Lin and
Meng Li and
Yuki Watanabe and
Taiki Kimura and
Tetsuaki Matsunawa and
Shigeki Nojima and
David Z. Pan},
title = {Data Efficient Lithography Modeling With Transfer Learning and Active
Data Selection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1900--1913},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864251},
doi = {10.1109/TCAD.2018.2864251},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Lin0WKMNP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinH19,
author = {Han{-}Yi Lin and
Jen{-}Wei Hsieh},
title = {Revive Bad Flash-Memory Pages by {HLC} Scheme},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {860--873},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834420},
doi = {10.1109/TCAD.2018.2834420},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinSZ19,
author = {Zhe Lin and
Sharad Sinha and
Wei Zhang},
title = {An Ensemble Learning Approach for In-Situ Monitoring of {FPGA} Dynamic
Power},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1661--1674},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859248},
doi = {10.1109/TCAD.2018.2859248},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinSZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuLCWWY19,
author = {Chin{-}Heng Liu and
Chia{-}Chun Lin and
Yung{-}Chih Chen and
Chia{-}Cheng Wu and
Chun{-}Yao Wang and
Shigeru Yamashita},
title = {Threshold Function Identification by Redundancy Removal and Comprehensive
Weight Assignments},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2284--2297},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878181},
doi = {10.1109/TCAD.2018.2878181},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuLCWWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYLCDVSP19,
author = {Derong Liu and
Bei Yu and
Vinicius S. Livramento and
Salim Chowdhury and
Duo Ding and
Huy Vo and
Akshay Sharma and
David Z. Pan},
title = {Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical
Signal Groups},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1147--1160},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834424},
doi = {10.1109/TCAD.2018.2834424},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYLCDVSP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYLCY19,
author = {Weichen Liu and
Juan Yi and
Mengquan Li and
Peng Chen and
Lei Yang},
title = {Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed
MPSoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {1--14},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801242},
doi = {10.1109/TCAD.2018.2801242},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYLCY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYLSLWFZ19,
author = {Dajiang Liu and
Shouyi Yin and
Guojie Luo and
Jiaxing Shang and
Leibo Liu and
Shaojun Wei and
Yong Feng and
Shangbo Zhou},
title = {Data-Flow Graph Mapping Optimization for {CGRA} With Deep Reinforcement
Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2271--2283},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878183},
doi = {10.1109/TCAD.2018.2878183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYLSLWFZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZYW19,
author = {Leibo Liu and
Wenping Zhu and
Shouyi Yin and
Shaojun Wei},
title = {A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s
Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1265--1277},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846634},
doi = {10.1109/TCAD.2018.2846634},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuCYLWL19,
author = {Hang Lu and
Yisong Chang and
Guihai Yan and
Ning Lin and
Xin Wei and
Xiaowei Li},
title = {ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core
Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1438--1451},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855165},
doi = {10.1109/TCAD.2018.2855165},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuCYLWL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuoFDC19,
author = {Chao Luo and
Yunsi Fei and
Aidong Adam Ding and
Pau Closas},
title = {Comprehensive Side-Channel Power Analysis of {XTS-AES}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2191--2200},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878171},
doi = {10.1109/TCAD.2018.2878171},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuoFDC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LyuQCM19,
author = {Yangdi Lyu and
Xiaoke Qin and
Mingsong Chen and
Prabhat Mishra},
title = {Directed Test Generation for Validation of Cache Coherence Protocols},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {163--176},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801239},
doi = {10.1109/TCAD.2018.2801239},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LyuQCM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaRMCY19,
author = {Yuzhe Ma and
Subhendu Roy and
Jin Miao and
Jiamin Chen and
Bei Yu},
title = {Cross-Layer Optimization for High Speed Adders: {A} Pareto Driven
Machine Learning Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2298--2311},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878129},
doi = {10.1109/TCAD.2018.2878129},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaRMCY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaSWS19,
author = {Chenlin Ma and
Zhaoyan Shen and
Yi Wang and
Zili Shao},
title = {Alleviating Hot Data Write Back Effect for Shingled Magnetic Recording
Storage Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2243--2254},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878190},
doi = {10.1109/TCAD.2018.2878190},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaSWS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MachaIR19,
author = {Naveen Kumar Macha and
Md Arif Iqbal and
Mostafizur Rahman},
title = {New 3-D {CMOS} Fabric With Stacked Horizontal Nanowires},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1625--1634},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2848588},
doi = {10.1109/TCAD.2018.2848588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MachaIR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MandalM19,
author = {Joydeb Mandal and
Mrinal Kanti Mandal},
title = {Computer-Aided Design of a Switchable True Time Delay {(TTD)} Line
With Shunt Open-Stubs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {430--438},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818731},
doi = {10.1109/TCAD.2018.2818731},
timestamp = {Mon, 21 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MandalM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaoZWJCY19,
author = {Bo Mao and
Jindong Zhou and
Suzhen Wu and
Hong Jiang and
Xiao Chen and
Weijian Yang},
title = {Improving Flash Memory Performance and Reliability for Smartphones
With {I/O} Deduplication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1017--1027},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834395},
doi = {10.1109/TCAD.2018.2834395},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaoZWJCY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MartinsLPPCRCSF19,
author = {Ricardo Martins and
Nuno Louren{\c{c}}o and
F{\'{a}}bio Passos and
Ricardo Povoa and
Ant{\'{o}}nio Canelas and
Elisenda Roca and
Rafael Castro{-}L{\'{o}}pez and
Javier J. Sieiro and
Francisco V. Fern{\'{a}}ndez and
Nuno Horta},
title = {Two-Step {RF} {IC} Block Synthesis With Preoptimized Inductors and
Full Layout Generation In-the-Loop},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {989--1002},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834394},
doi = {10.1109/TCAD.2018.2834394},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MartinsLPPCRCSF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MatosCR19,
author = {Jody Maick Matos and
Jordi Carrabina and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Efficiently Mapping {VLSI} Circuits With Simple Cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {692--704},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818709},
doi = {10.1109/TCAD.2018.2818709},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MatosCR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoghaddamMRSTZ19,
author = {Elham K. Moghaddam and
Nilanjan Mukherjee and
Janusz Rajski and
Jedrzej Solecki and
Jerzy Tyszer and
Justyna Zawada},
title = {Logic {BIST} With Capture-Per-Clock Hybrid Test Points},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1028--1041},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834441},
doi = {10.1109/TCAD.2018.2834441},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoghaddamMRSTZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoghaddasiFSK19,
author = {Iraj Moghaddasi and
Arash Fouman and
Mostafa E. Salehi and
Mehdi Kargahi},
title = {Instruction-Level {NBTI} Stress Estimation and Its Application in
Runtime Aging Prediction for Embedded Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1427--1437},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846629},
doi = {10.1109/TCAD.2018.2846629},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoghaddasiFSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MurraySBC19,
author = {Kevin E. Murray and
Andrea Suardi and
Vaughn Betz and
George A. Constantinides},
title = {Calculated Risks: Quantifying Timing Error Probability With Extended
Static Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {719--732},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2821563},
doi = {10.1109/TCAD.2018.2821563},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MurraySBC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NahiyanFMFT19,
author = {Adib Nahiyan and
Farimah Farahmandi and
Prabhat Mishra and
Domenic Forte and
Mark M. Tehranipoor},
title = {Security-Aware {FSM} Design Flow for Identifying and Mitigating Vulnerabilities
to Fault Attacks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1003--1016},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834396},
doi = {10.1109/TCAD.2018.2834396},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NahiyanFMFT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NeutzlingMMRR19,
author = {Augusto Neutzling and
Jody Maick Matos and
Alan Mishchenko and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Effective Logic Synthesis for Threshold Logic Circuit Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {926--937},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834434},
doi = {10.1109/TCAD.2018.2834434},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NeutzlingMMRR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NikkhahZKAP19,
author = {Shayan Tabatabaei Nikkhah and
Mahdi Zahedi and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {{ACHILLES:} Accuracy-Aware High-Level Synthesis Considering Online
Quality Management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1452--1465},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846625},
doi = {10.1109/TCAD.2018.2846625},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NikkhahZKAP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ONealBSK19,
author = {Kenneth O'Neal and
Philip Brisk and
Emily Shriver and
Michael Kishinevsky},
title = {Hardware-Assisted Cross-Generation Prediction of GPUs Under Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1133--1146},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834398},
doi = {10.1109/TCAD.2018.2834398},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ONealBSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PagliariDCBMP19,
author = {Daniele Jahier Pagliari and
Yves Durand and
David Coriat and
Edith Beign{\'{e}} and
Enrico Macii and
Massimo Poncino},
title = {Fine-Grain Back Biasing for the Design of Energy-Quality Scalable
Operators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1042--1055},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834400},
doi = {10.1109/TCAD.2018.2834400},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PagliariDCBMP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkK19,
author = {Dawon Park and
Younghyun Kim},
title = {Fast Pareto Front Exploration for Design of Reconfigurable Energy
Storage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {526--537},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818711},
doi = {10.1109/TCAD.2018.2818711},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PilatoWGKR19,
author = {Christian Pilato and
Kaijie Wu and
Siddharth Garg and
Ramesh Karri and
Francesco Regazzoni},
title = {TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {798--808},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834421},
doi = {10.1109/TCAD.2018.2834421},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PilatoWGKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PlovieVVQB19,
author = {Bart Plovie and
Jan Vanfleteren and
Thomas Vervust and
Andr{\'{e}}s V{\'{a}}squez Quintero and
Frederick Bossuyt},
title = {Design Automation of Meandered Interconnects for Stretchable Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1648--1660},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859222},
doi = {10.1109/TCAD.2018.2859222},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PlovieVVQB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PoddarBNCB19,
author = {Sudip Poddar and
Sukanta Bhattacharjee and
Subhas C. Nandy and
Krishnendu Chakrabarty and
Bhargab B. Bhattacharya},
title = {Optimization of Multi-Target Sample Preparation On-Demand With Digital
Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {253--266},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808234},
doi = {10.1109/TCAD.2018.2808234},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PoddarBNCB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PoddarWRB19,
author = {Sudip Poddar and
Robert Wille and
Hafizur Rahaman and
Bhargab B. Bhattacharya},
title = {Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1886--1899},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864263},
doi = {10.1109/TCAD.2018.2864263},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PoddarWRB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19,
author = {Irith Pomeranz},
title = {Diagnostic Test Generation That Addresses Diagnostic Holes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {335--344},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812121},
doi = {10.1109/TCAD.2018.2812121},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19a,
author = {Irith Pomeranz},
title = {LFSR-Based Test Generation for Path Delay Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {345--353},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812120},
doi = {10.1109/TCAD.2018.2812120},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19b,
author = {Irith Pomeranz},
title = {Skewed-Load Tests for Transition and Stuck-at Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1969--1973},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2873233},
doi = {10.1109/TCAD.2018.2873233},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19c,
author = {Irith Pomeranz},
title = {Invisible-Scan: {A} Design-for-Testability Approach for Functional
Test Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2357--2365},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878176},
doi = {10.1109/TCAD.2018.2878176},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PradhanBCB19,
author = {Manjari Pradhan and
Bhaswar B. Bhattacharya and
Krishnendu Chakrabarty and
Bhargab B. Bhattacharya},
title = {Predicting X-Sensitivity of Circuit-Inputs on Test-Coverage: {A} Machine-Learning
Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2343--2356},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878169},
doi = {10.1109/TCAD.2018.2878169},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PradhanBCB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QureshiH19,
author = {Amina Qureshi and
Osman Hasan},
title = {Formal Probabilistic Analysis of Low Latency Approximate Adders},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {177--189},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2803622},
doi = {10.1109/TCAD.2018.2803622},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QureshiH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Rangel-PatinoRV19,
author = {Francisco E. Rangel{-}Patino and
Jos{\'{e}} Ernesto Rayas{-}S{\'{a}}nchez and
Andres Viveros{-}Wacher and
Jos{\'{e}} Luis Chavez{-}Hurtado and
Edgar{-}Andrei Vega{-}Ochoa and
Nagib Hakim},
title = {Post-Silicon Receiver Equalization Metamodeling by Artificial Neural
Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {733--740},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834403},
doi = {10.1109/TCAD.2018.2834403},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Rangel-PatinoRV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RathiP019,
author = {Nitin Rathi and
Priyadarshini Panda and
Kaushik Roy},
title = {STDP-Based Pruning of Connections and Weight Quantization in Spiking
Neural Networks for Energy-Efficient Recognition},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {668--677},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2819366},
doi = {10.1109/TCAD.2018.2819366},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RathiP019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RenTBT19,
author = {Xuanle Ren and
Francisco Pimentel Torres and
Ronald D. Blanton and
V{\'{\i}}tor Grade Tavares},
title = {{IC} Protection Against JTAG-Based Attacks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {149--162},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2802866},
doi = {10.1109/TCAD.2018.2802866},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RenTBT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RokickiRD19,
author = {Simon Rokicki and
Erven Rohou and
Steven Derrien},
title = {Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting
{VLIW}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1872--1885},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864288},
doi = {10.1109/TCAD.2018.2864288},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RokickiRD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RosaBB19,
author = {Leandro de Souza Rosa and
Christos{-}Savvas Bouganis and
Vanderlei Bonato},
title = {Scaling Up Modulo Scheduling for High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {912--925},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834440},
doi = {10.1109/TCAD.2018.2834440},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RosaBB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SafaeiWTY19,
author = {Amin Safaei and
Q. M. Jonathan Wu and
Akilan Thangarajah and
Yimin Yang},
title = {System-on-a-Chip (SoC)-Based Hardware Acceleration for an Online Sequential
Extreme Learning Machine {(OS-ELM)}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2127--2138},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878162},
doi = {10.1109/TCAD.2018.2878162},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SafaeiWTY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SafieddineZKER19,
author = {Maya H. Safieddine and
Fadi A. Zaraket and
Rouwaida Kanj and
Ali S. Elzein and
Wolfgang Roesner},
title = {Verification at {RTL} Using Separation of Design Concerns},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1529--1542},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2848589},
doi = {10.1109/TCAD.2018.2848589},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SafieddineZKER19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SahinTC19,
author = {Onur Sahin and
Lothar Thiele and
Ayse K. Coskun},
title = {Maestro: Autonomous QoS Management for Mobile Applications Under Thermal
Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1557--1570},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855180},
doi = {10.1109/TCAD.2018.2855180},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SahinTC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchneiderW19,
author = {Eric Schneider and
Hans{-}Joachim Wunderlich},
title = {{SWIFT:} Switch-Level Fault Simulation on GPUs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {122--135},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2802871},
doi = {10.1109/TCAD.2018.2802871},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchneiderW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeitanidisDMMC19,
author = {Ioannis Seitanidis and
Giorgos Dimitrakopoulos and
Pavlos M. Mattheakis and
Laurent Masse{-}Navette and
David G. Chinnery},
title = {Timing-Driven and Placement-Aware Multibit Register Composition},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1501--1514},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2852740},
doi = {10.1109/TCAD.2018.2852740},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeitanidisDMMC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeitanidisND19,
author = {Ioannis Seitanidis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Automatic Generation of Peak-Power Traffic for Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {96--108},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801223},
doi = {10.1109/TCAD.2018.2801223},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SeitanidisND19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaKR19,
author = {Anirban Sengupta and
Deepak Kachave and
Dipanjan Roy},
title = {Low Cost Functional Obfuscation of Reusable {IP} Ores Used in {CE}
Hardware Through Robust Locking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {604--616},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818720},
doi = {10.1109/TCAD.2018.2818720},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaSHS19,
author = {Deepashree Sengupta and
Farhana Sharmin Snigdha and
Jiang Hu and
Sachin S. Sapatnekar},
title = {An Analytical Approach for Error {PMF} Characterization in Approximate
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {70--83},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2803626},
doi = {10.1109/TCAD.2018.2803626},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaSHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShayanTCK19,
author = {Mohammed Shayan and
Jack Tang and
Krishnendu Chakrabarty and
Ramesh Karri},
title = {Security Assessment of Micro-Electrode-Dot-Array Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1831--1843},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864249},
doi = {10.1109/TCAD.2018.2864249},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShayanTCK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShenSSG19,
author = {Zhaoyan Shen and
Yuanjing Shi and
Zili Shao and
Yong Guan},
title = {An Efficient LSM-Tree-Based SQLite-Like Database Engine for Mobile
Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1635--1647},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855179},
doi = {10.1109/TCAD.2018.2855179},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShenSSG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiTF19,
author = {Qihang Shi and
Mark M. Tehranipoor and
Domenic Forte},
title = {Obfuscated Built-In Self-Authentication With Secure and Efficient
Wire-Lifting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {1981--1994},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2877012},
doi = {10.1109/TCAD.2018.2877012},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShiTF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SilvaFNR19,
author = {Mathieu Da Silva and
Marie{-}Lise Flottes and
Giorgio Di Natale and
Bruno Rouzeyre},
title = {Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {538--550},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818722},
doi = {10.1109/TCAD.2018.2818722},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SilvaFNR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinglaA0M19,
author = {Ananya Singla and
Varsha Agarwal and
Sudip Roy and
Arijit Mondal},
title = {Reliability Analysis of Mixture Preparation Using Digital Microfluidic
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {654--667},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2819081},
doi = {10.1109/TCAD.2018.2819081},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinglaA0M19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SnigdhaSHS19,
author = {Farhana Sharmin Snigdha and
Deepashree Sengupta and
Jiang Hu and
Sachin S. Sapatnekar},
title = {Dynamic Approximation of {JPEG} Hardware},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {295--308},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808224},
doi = {10.1109/TCAD.2018.2808224},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SnigdhaSHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SoekenRWM19,
author = {Mathias Soeken and
Martin Roetteler and
Nathan Wiebe and
Giovanni De Micheli},
title = {LUT-Based Hierarchical Reversible Logic Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1675--1688},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2859251},
doi = {10.1109/TCAD.2018.2859251},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SoekenRWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuC19,
author = {Yu{-}Hsuan Su and
Yao{-}Wen Chang},
title = {DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {267--280},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812122},
doi = {10.1109/TCAD.2018.2812122},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TamimiEKA19,
author = {Sajjad Tamimi and
Zahra Ebrahimi and
Behnam Khaleghi and
Hossein Asadi},
title = {An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {466--479},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812118},
doi = {10.1109/TCAD.2018.2812118},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TamimiEKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangICK19,
author = {Jack Tang and
Mohamed Ibrahim and
Krishnendu Chakrabarty and
Ramesh Karri},
title = {Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {589--603},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855132},
doi = {10.1109/TCAD.2018.2855132},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangICK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TaoSZZL19,
author = {Jun Tao and
Yangfeng Su and
Dian Zhou and
Xuan Zeng and
Xin Li},
title = {Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization
via {SDP} Relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1385--1398},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2848590},
doi = {10.1109/TCAD.2018.2848590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TaoSZZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TasoulasAPS19,
author = {Zois{-}Gerasimos Tasoulas and
Iraklis Anagnostopoulos and
Lazaros Papadopoulos and
Dimitrios Soudris},
title = {A Message-Passing Microcoded Synchronization for Distributed Shared
Memory Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {975--979},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834423},
doi = {10.1109/TCAD.2018.2834423},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TasoulasAPS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TeimouriTS19,
author = {Nasibeh Teimouri and
Hamed Tabkhi and
Gunar Schirner},
title = {Alleviating Scalability Limitation of Accelerator-Based Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1317--1330},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846632},
doi = {10.1109/TCAD.2018.2846632},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TeimouriTS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TianWXLYM19,
author = {Zhongyuan Tian and
Zhe Wang and
Jiang Xu and
Haoran Li and
Peng Yang and
Rafael Kioji Vivas Maeda},
title = {Collaborative Power Management Through Knowledge Sharing Among Multiple
Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1203--1215},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2837131},
doi = {10.1109/TCAD.2018.2837131},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TianWXLYM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Wang0CQ19,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Toward a Formal and Quantitative Evaluation Framework for Circuit
Obfuscation Methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1844--1857},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864220},
doi = {10.1109/TCAD.2018.2864220},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Wang0CQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangAM19,
author = {Siqi Wang and
Gayathri Ananthanarayanan and
Tulika Mitra},
title = {OPTiC: Optimizing Collaborative {CPU-GPU} Computing on Mobile Devices
With Thermal Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {393--406},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2873210},
doi = {10.1109/TCAD.2018.2873210},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangAM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangCT19,
author = {Shengcheng Wang and
Krishnendu Chakrabarty and
Mehdi Baradaran Tahoori},
title = {Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield
Enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1928--1941},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864291},
doi = {10.1109/TCAD.2018.2864291},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangCT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangGZC19,
author = {Kan Wang and
Yong Gu and
Tong Zhou and
Hao Chen},
title = {Multi-Pair Active Shielding for Security {IC} Protection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2321--2329},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878175},
doi = {10.1109/TCAD.2018.2878175},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangGZC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHLZTY19,
author = {Hai Wang and
Darong Huang and
Rui Liu and
Chi Zhang and
He Tang and
Yuan Yuan},
title = {{STREAM:} Stress and Thermal Aware Reliability Management for 3-D
ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2058--2071},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2877019},
doi = {10.1109/TCAD.2018.2877019},
timestamp = {Wed, 01 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangHLZTY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHYL19,
author = {Yi Wang and
Jiangfan Huang and
Jing Yang and
Tao Li},
title = {A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap
Flash Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {234--244},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808227},
doi = {10.1109/TCAD.2018.2808227},
timestamp = {Wed, 15 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLLHLWYWM19,
author = {Liang Wang and
Ping Lv and
Leibo Liu and
Jie Han and
Ho{-}fung Leung and
Xiaohang Wang and
Shouyi Yin and
Shaojun Wei and
Terrence S. T. Mak},
title = {A Lifetime Reliability-Constrained Runtime Mapping for Throughput
Optimization in Many-Core Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1771--1784},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855168},
doi = {10.1109/TCAD.2018.2855168},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLLHLWYWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangR19,
author = {Xiaowen Wang and
William H. Robinson},
title = {Error Estimation and Error Reduction With Input-Vector Profiling for
Timing Speculation in Digital Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {385--389},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808240},
doi = {10.1109/TCAD.2018.2808240},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangSLS19,
author = {Tianchen Wang and
Sandeep Kumar Samal and
Sung Kyu Lim and
Yiyu Shi},
title = {Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to
Mobile Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {84--95},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2803623},
doi = {10.1109/TCAD.2018.2803623},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangSLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangWLM19,
author = {Liang Wang and
Xiaohang Wang and
Ho{-}fung Leung and
Terrence S. T. Mak},
title = {A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1373--1377},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855149},
doi = {10.1109/TCAD.2018.2855149},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangWLM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WenXYYZH19,
author = {Shiping Wen and
Shuixin Xiao and
Yin Yang and
Zheng Yan and
Zhigang Zeng and
Tingwen Huang},
title = {Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks
via Fuzzy Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1084--1094},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834436},
doi = {10.1109/TCAD.2018.2834436},
timestamp = {Tue, 07 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WenXYYZH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WillseyLCBC19,
author = {Max Willsey and
Vincent T. Lee and
Alvin Cheung and
Rastislav Bod{\'{\i}}k and
Luis Ceze},
title = {Iterative Search for Reconfigurable Accelerator Blocks With a Compiler
in the Loop},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {407--418},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878194},
doi = {10.1109/TCAD.2018.2878194},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WillseyLCBC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WolfsonH19,
author = {Scott C. Wolfson and
Fat D. Ho},
title = {2-D Modeling of Dual-Gate {MOSFET} Devices Using Quintic Splines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {480--488},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818714},
doi = {10.1109/TCAD.2018.2818714},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WolfsonH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuLMCL19,
author = {Suzhen Wu and
Haijun Li and
Bo Mao and
Xiaoxi Chen and
Kuan{-}Ching Li},
title = {Overcome the GC-Induced Performance Variability in SSD-Based RAIDs
With Request Redirection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {822--833},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834407},
doi = {10.1109/TCAD.2018.2834407},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuLMCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiaLNCW19,
author = {Lixue Xia and
Mengyun Liu and
Xuefei Ning and
Krishnendu Chakrabarty and
Yu Wang},
title = {Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based
Neural Computing Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1611--1624},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855145},
doi = {10.1109/TCAD.2018.2855145},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiaLNCW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieS19,
author = {Yang Xie and
Ankur Srivastava},
title = {Anti-SAT: Mitigating {SAT} Attack on Logic Locking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {199--207},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2801220},
doi = {10.1109/TCAD.2018.2801220},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XieS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieZKTLLL19,
author = {Guoqi Xie and
Gang Zeng and
Ryo Kurachi and
Hiroaki Takada and
Zhetao Li and
Renfa Li and
Keqin Li},
title = {{WCRT} Analysis and Evaluation for Sporadic Message-Processing Tasks
in Multicore Automotive Gateways},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {281--294},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812119},
doi = {10.1109/TCAD.2018.2812119},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieZKTLLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuCLM19,
author = {Yin Xu and
Zhijian Chen and
Feiteng Li and
Jianyi Meng},
title = {A Granular Resampling Method and Adaptive Speculative Mechanism-Based
Energy-Efficient Architecture for Multiclass Heartbeat Classification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2172--2176},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2871819},
doi = {10.1109/TCAD.2018.2871819},
timestamp = {Fri, 23 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuCLM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuLXYSZH19,
author = {Xiaowei Xu and
Feng Lin and
Wenyao Xu and
Xinwei Yao and
Yiyu Shi and
Dewen Zeng and
Yu Hu},
title = {{MDA:} {A} Reconfigurable Memristor-Based Distance Accelerator for
Time Series Mining on Data Centers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {785--797},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834431},
doi = {10.1109/TCAD.2018.2834431},
timestamp = {Wed, 05 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuLXYSZH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Yan19,
author = {Jin{-}Tai Yan},
title = {Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed
{PCB} Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {512--525},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818728},
doi = {10.1109/TCAD.2018.2818728},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Yan19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Yan19a,
author = {Jin{-}Tai Yan},
title = {Single-Layer {GNR} Routing for Minimization of Bending Delay},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2099--2112},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878164},
doi = {10.1109/TCAD.2018.2878164},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Yan19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangSLS19,
author = {Zhiyuan Yang and
Caleb Serafy and
Tiantao Lu and
Ankur Srivastava},
title = {Enhanced Phase-Driven Q-Learning-Based {DRM} for Multicore Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2022--2031},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2877014},
doi = {10.1109/TCAD.2018.2877014},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YangSLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangSZMYY19,
author = {Haoyu Yang and
Jing Su and
Yi Zou and
Yuzhe Ma and
Bei Yu and
Evangeline F. Y. Young},
title = {Layout Hotspot Detection With Feature Tensor Generation and Deep Biased
Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1175--1187},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2837078},
doi = {10.1109/TCAD.2018.2837078},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangSZMYY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangWTZKZR19,
author = {Tao Yang and
Yadong Wei and
Zhijun Tu and
Haolun Zeng and
Michel A. Kinsy and
Nanning Zheng and
Pengju Ren},
title = {Design Space Exploration of Neural Network Activation Function Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1974--1978},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2871198},
doi = {10.1109/TCAD.2018.2871198},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangWTZKZR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangWZWLCZ19,
author = {Jianlei Yang and
Xueyan Wang and
Qiang Zhou and
Zhaohao Wang and
Hai Li and
Yiran Chen and
Weisheng Zhao},
title = {Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit
Obfuscation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {57--69},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2802870},
doi = {10.1109/TCAD.2018.2802870},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangWZWLCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YesilBK19,
author = {Abdullah Yesil and
Yunus Babacan and
Firat Ka{\c{c}}ar},
title = {Design and Experimental Evolution of Memristor With Only One {VDTA}
and One Capacitor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {6},
pages = {1123--1132},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834399},
doi = {10.1109/TCAD.2018.2834399},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YesilBK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiBNJCL19,
author = {Maoxiang Yi and
Jingchang Bian and
Tianming Ni and
Cuiyun Jiang and
Hao Chang and
Huaguo Liang},
title = {A Pulse Shrinking-Based Test Solution for Prebond Through Silicon
via in 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {755--766},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2821559},
doi = {10.1109/TCAD.2018.2821559},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiBNJCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinTLOTLW19,
author = {Shouyi Yin and
Shibin Tang and
Xinhan Lin and
Peng Ouyang and
Fengbin Tu and
Leibo Liu and
Shaojun Wei},
title = {A High Throughput Acceleration for Hybrid Neural Networks With Efficient
Resource Management on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {678--691},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2821561},
doi = {10.1109/TCAD.2018.2821561},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YinTLOTLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuC19,
author = {Cunxi Yu and
Maciej J. Ciesielski},
title = {Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification
and Reverse Engineering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {354--365},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2808457},
doi = {10.1109/TCAD.2018.2808457},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanCWZXH19,
author = {Junqi Yuan and
Jialing Chen and
Lingli Wang and
Xuegong Zhou and
Yinshui Xia and
Jianping Hu},
title = {{ARBSA:} Adaptive Range-Based Simulated Annealing for {FPGA} Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2330--2342},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878180},
doi = {10.1109/TCAD.2018.2878180},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuanCWZXH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZacharopoulosFG19,
author = {Georgios Zacharopoulos and
Lorenzo Ferretti and
Emanuele Giaquinta and
Giovanni Ansaloni and
Laura Pozzi},
title = {RegionSeeker: Automatically Identifying and Selecting Accelerators
From Application Source Code},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {741--754},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818689},
doi = {10.1109/TCAD.2018.2818689},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZacharopoulosFG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhanLS19,
author = {Xin Zhan and
Peng Li and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {Taming the Stability-Constrained Performance Optimization Challenge
of Distributed On-Chip Voltage Regulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {8},
pages = {1571--1584},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855173},
doi = {10.1109/TCAD.2018.2855173},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhanLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Zhang0SHS19,
author = {Grace Li Zhang and
Bing Li and
Yiyu Shi and
Jiang Hu and
Ulf Schlichtmann},
title = {EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock
Skew Configuration Under Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {705--718},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818713},
doi = {10.1109/TCAD.2018.2818713},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Zhang0SHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangCL19,
author = {Wenhui Zhang and
Qiang Cao and
Zhonghai Lu},
title = {Bit-Flipping Schemes Upon {MLC} Flash: Investigation, Implementation,
and Evaluation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {780--784},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818693},
doi = {10.1109/TCAD.2018.2818693},
timestamp = {Mon, 13 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangSFZPC19,
author = {Chen Zhang and
Guangyu Sun and
Zhenman Fang and
Peipei Zhou and
Peichen Pan and
Jason Cong},
title = {Caffeine: Toward Uniformed Representation and Acceleration for Deep
Convolutional Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2072--2085},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2017.2785257},
doi = {10.1109/TCAD.2017.2785257},
timestamp = {Fri, 05 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangSFZPC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangWDLX19,
author = {Meng Zhang and
Fei Wu and
Yajuan Du and
Weihua Liu and
Changsheng Xie},
title = {Pair-Bit Errors Aware {LDPC} Decoding in {MLC} {NAND} Flash Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2312--2320},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878132},
doi = {10.1109/TCAD.2018.2878132},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangWDLX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangWLCLWLW19,
author = {Feilong Zhang and
Chenkun Wang and
Fei Lu and
Qi Chen and
Cheng Li and
X. Shawn Wang and
Daguang Li and
Albert Z. Wang},
title = {A Full-Chip {ESD} Protection Circuit Simulation and Fast Dynamic Checking
Method Using {SPICE} and {ESD} Behavior Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {3},
pages = {489--498},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2818707},
doi = {10.1109/TCAD.2018.2818707},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangWLCLWLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoSZ0YHGYL19,
author = {Qinghang Zhao and
Wenyu Sun and
Jiaqing Zhao and
Jian Zhao and
Hailong Yao and
Tsung{-}Yi Ho and
Xiaojun Guo and
Huazhong Yang and
Yongpan Liu},
title = {Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer
Interconnection Architecture and Optimization Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {11},
pages = {2043--2057},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878185},
doi = {10.1109/TCAD.2018.2878185},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoSZ0YHGYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouDZZLL0GCC19,
author = {Xuda Zhou and
Zidong Du and
Shijin Zhang and
Lei Zhang and
Huiying Lan and
Shaoli Liu and
Ling Li and
Qi Guo and
Tianshi Chen and
Yunji Chen},
title = {Addressing Sparsity in Deep Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1858--1871},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864289},
doi = {10.1109/TCAD.2018.2864289},
timestamp = {Sat, 28 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhouDZZLL0GCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouSZWCHH19,
author = {Junlong Zhou and
Jin Sun and
Xiumin Zhou and
Tongquan Wei and
Mingsong Chen and
Shiyan Hu and
Xiaobo Sharon Hu},
title = {Resource Management for Improving Soft-Error and Lifetime Reliability
of Real-Time MPSoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2215--2228},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2883993},
doi = {10.1109/TCAD.2018.2883993},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhouSZWCHH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuDY19,
author = {Weijun Zhu and
Gang Dong and
Yintang Yang},
title = {Thermal-Aware Modeling and Analysis for a Power Distribution Network
Including Through-Silicon-Vias in 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1278--1290},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846659},
doi = {10.1109/TCAD.2018.2846659},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuDY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuoUSS19,
author = {Cheng Zhuo and
Kassan Unda and
Yiyu Shi and
Wei{-}Kai Shih},
title = {From Layout to System: Early Stage Power Delivery and Architecture
Co-Exploration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1291--1304},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834438},
doi = {10.1109/TCAD.2018.2834438},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhuoUSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Zivkovic0OSB19,
author = {Carna Zivkovic and
Christoph Grimm and
Markus Olbrich and
Oliver Scharf and
Erich Barke},
title = {Hierarchical Verification of {AMS} Systems With Affine Arithmetic
Decision Diagrams},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1785--1798},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864238},
doi = {10.1109/TCAD.2018.2864238},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Zivkovic0OSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZulehnerPW19,
author = {Alwin Zulehner and
Alexandru Paler and
Robert Wille},
title = {An Efficient Methodology for Mapping Quantum Circuits to the {IBM}
{QX} Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1226--1236},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846658},
doi = {10.1109/TCAD.2018.2846658},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZulehnerPW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZulehnerW19,
author = {Alwin Zulehner and
Robert Wille},
title = {Advanced Simulation of Quantum Computations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {848--859},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834427},
doi = {10.1109/TCAD.2018.2834427},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZulehnerW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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