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@article{DBLP:journals/tcad/000210,
author = {Hao Zheng},
title = {Compositional Reachability Analysis for Efficient Modular Verification
of Asynchronous Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {329--340},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035544},
doi = {10.1109/TCAD.2009.2035544},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/000210.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/0002Y10,
author = {Qiang Ma and
Evangeline F. Y. Young},
title = {Multivoltage Floorplan Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {607--617},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042895},
doi = {10.1109/TCAD.2010.2042895},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/0002Y10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AcaryBB10,
author = {Vincent Acary and
Olivier Bonnefon and
Bernard Brogliato},
title = {Time-Stepping Numerical Simulation of Switched Circuits Within the
Nonsmooth Dynamical Systems Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1042--1055},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049134},
doi = {10.1109/TCAD.2010.2049134},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcaryBB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlizadehF10,
author = {Bijan Alizadeh and
Masahiro Fujita},
title = {Modular Datapath Optimization and Verification Based on Modular-HED},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1422--1435},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2059271},
doi = {10.1109/TCAD.2010.2059271},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlizadehF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlizadehMF10,
author = {Bijan Alizadeh and
Mohammad Mirzaei and
Masahiro Fujita},
title = {Coverage Driven High-Level Test Generation Using a Polynomial Model
of Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {737--748},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043571},
doi = {10.1109/TCAD.2010.2043571},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlizadehMF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpaslanHLCD10,
author = {Elif Alpaslan and
Yu Huang and
Xijiang Lin and
Wu{-}Tung Cheng and
Jennifer Dworak},
title = {On Reducing Scan Shift Activity at {RTL}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1110--1120},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049057},
doi = {10.1109/TCAD.2010.2049057},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpaslanHLCD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlvesBNDB10,
author = {Nuno Alves and
Alison Buben and
Kundan Nepal and
Jennifer Dworak and
R. Iris Bahar},
title = {A Cost Effective Approach for Online Error Detection Using Invariant
Relationships},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {788--801},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043590},
doi = {10.1109/TCAD.2010.2043590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlvesBNDB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AndriamisainaCCC10,
author = {Caaliph Andriamisaina and
Philippe Coussy and
Emmanuel Casseau and
Cyrille Chavet},
title = {High-Level Synthesis for Designing Multimode Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1736--1749},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2062751},
doi = {10.1109/TCAD.2010.2062751},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AndriamisainaCCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ArjomandS10,
author = {Mohammad Arjomand and
Hamid Sarbazi{-}Azad},
title = {Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer
Allocation Schemes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1558--1571},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061171},
doi = {10.1109/TCAD.2010.2061171},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ArjomandS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BallicchiaO10,
author = {Mauro Ballicchia and
Simone Orcioni},
title = {Design and Modeling of Optimum Quality Spiral Inductors With Regularization
and Debye Approximation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1669--1681},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061470},
doi = {10.1109/TCAD.2010.2061470},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BallicchiaO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BayrakciDT10,
author = {Alp Arslan Bayrakci and
Alper Demir and
Serdar Tasiran},
title = {Fast Monte Carlo Estimation of Timing Yield With Importance Sampling
and Transistor-Level Circuit Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1328--1341},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049042},
doi = {10.1109/TCAD.2010.2049042},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BayrakciDT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeltrameFS10,
author = {Giovanni Beltrame and
Luca Fossati and
Donatella Sciuto},
title = {Decision-Theoretic Design Space Exploration of Multiprocessor Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1083--1095},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049053},
doi = {10.1109/TCAD.2010.2049053},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeltrameFS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeygiD10,
author = {Amir Beygi and
Anestis Dounavis},
title = {Sensitivity Analysis of Lossy Multiconductor Transmission Lines Based
on the Passive Method of Characteristics Macromodel},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1290--1294},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2046810},
doi = {10.1109/TCAD.2010.2046810},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeygiD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BloemS10,
author = {Roderick Bloem and
Patrick Schaumont},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1457--1458},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2060170},
doi = {10.1109/TCAD.2010.2060170},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BloemS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Bohm10,
author = {Peter B{\"{o}}hm},
title = {Incremental and Verified Modeling of the {PCI} Express Protocol},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1495--1508},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2054990},
doi = {10.1109/TCAD.2010.2054990},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Bohm10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BondMLSMSAD10,
author = {Bradley N. Bond and
Zohaib Mahmood and
Yan Li and
Ranko Sredojevic and
Alexandre Megretski and
Vladimir Stojanovic and
Yehuda Avniel and
Luca Daniel},
title = {Compact Modeling of Nonlinear Analog Circuits Using System Identification
via Semidefinite Programming and Incremental Stability Certification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1149--1162},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049155},
doi = {10.1109/TCAD.2010.2049155},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BondMLSMSAD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrambillaGG10,
author = {Angelo Brambilla and
Giambattista Gruosso and
Giancarlo Storti Gajani},
title = {{FSSA:} Fast Steady-State Algorithm for the Analysis of Mixed Analog/Digital
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {528--537},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042886},
doi = {10.1109/TCAD.2010.2042886},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrambillaGG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BriandJ10,
author = {Xavier Briand and
Bertrand Jeannet},
title = {Combining Control and Data Abstraction in the Verification of Hybrid
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1481--1494},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2066010},
doi = {10.1109/TCAD.2010.2066010},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BriandJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BriskVI10,
author = {Philip Brisk and
Ajay Kumar Verma and
Paolo Ienne},
title = {An Optimal Linear-Time Algorithm for Interprocedural Register Allocation
in High Level Synthesis Using {SSA} Form},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1096--1109},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049060},
doi = {10.1109/TCAD.2010.2049060},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BriskVI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BroussevT10,
author = {Svetozar S. Broussev and
Nikolay T. Tchamov},
title = {Time-Varying Root-Locus of Large-Signal {LC} Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {830--834},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043592},
doi = {10.1109/TCAD.2010.2043592},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BroussevT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CabodiGMNQ10,
author = {Gianpiero Cabodi and
Luz Amanda Garcia and
Marco Murciano and
Sergio Nocco and
Stefano Quer},
title = {Partitioning Interpolant-Based Verification for Effective Unbounded
Model Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {382--395},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041847},
doi = {10.1109/TCAD.2010.2041847},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CabodiGMNQ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CauleyBK10,
author = {Stephen Cauley and
Venkataramanan Balakrishnan and
Cheng{-}Kok Koh},
title = {A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground
Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {636--641},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042901},
doi = {10.1109/TCAD.2010.2042901},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CauleyBK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabartyFZ10,
author = {Krishnendu Chakrabarty and
Richard B. Fair and
Jun Zeng},
title = {Design Tools for Digital Microfluidic Biochips: Toward Functional
Diversification and More Than Moore},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1001--1017},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049153},
doi = {10.1109/TCAD.2010.2049153},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabartyFZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabortySP10,
author = {Ashutosh Chakraborty and
Sean X. Shi and
David Z. Pan},
title = {Stress Aware Layout Optimization Leveraging Active Area Dependent
Mobility Enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1533--1545},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061173},
doi = {10.1109/TCAD.2010.2061173},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabortySP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangF10,
author = {Chip{-}Hong Chang and
Mathias Faust},
title = {On "A New Common Subexpression Elimination Algorithm for Realizing
Low-Complexity Higher Order Digital Filters"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {844--848},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043585},
doi = {10.1109/TCAD.2010.2043585},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangLGWW10,
author = {Yen{-}Jung Chang and
Yu{-}Ting Lee and
Jhih{-}Rong Gao and
Pei{-}Ci Wu and
Ting{-}Chi Wang},
title = {NTHU-Route 2.0: {A} Robust Global Router for Modern Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1931--1944},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061590},
doi = {10.1109/TCAD.2010.2061590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangLGWW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Chen10,
author = {Gang Chen},
title = {Formalization of a Parameterized Parallel Adder Within the Coq Theorem
Prover},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {149--153},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034346},
doi = {10.1109/TCAD.2009.2034346},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Chen10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCDHLP10,
author = {Deming Chen and
Jason Cong and
Chen Dong and
Lei He and
Fei Li and
Chi{-}Chen Peng},
title = {Technology Mapping and Clustering for {FPGA} Architectures With Dual
Supply Voltages},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1709--1722},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061770},
doi = {10.1109/TCAD.2010.2061770},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCDHLP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenHC10,
author = {Po{-}Lin Chen and
Yu{-}Chieh Huang and
Tsin{-}Yuan Chang},
title = {Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple
Clock Domains Based on {IEEE} Standard 1500},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1837--1842},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2055010},
doi = {10.1109/TCAD.2010.2055010},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenHC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenL10,
author = {Fu{-}Wei Chen and
Yi{-}Yu Liu},
title = {Performance-Driven Dual-Rail Routing Architecture for Structured {ASIC}
Design Style},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {2046--2050},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2063111},
doi = {10.1109/TCAD.2010.2063111},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLC10,
author = {Tai{-}Chen Chen and
Guang{-}Wan Liao and
Yao{-}Wen Chang},
title = {Predictive Formulae for {OPC} With Applications to Lithography-Friendly
Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {40--50},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2032359},
doi = {10.1109/TCAD.2009.2032359},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLW10,
author = {Jwu{-}E Chen and
Pei{-}Wen Luo and
Chin{-}Long Wey},
title = {Placement Optimization for Yield Improvement of Switched-Capacitor
Analog Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {313--318},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035587},
doi = {10.1109/TCAD.2009.2035587},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenLW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenM10,
author = {Mingsong Chen and
Prabhat Mishra},
title = {Functional Test Generation Using Efficient Property Clustering and
Learning Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {396--404},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041846},
doi = {10.1109/TCAD.2010.2041846},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenSMV10,
author = {Yibin Chen and
Sean Safarpour and
Jo{\~{a}}o Marques{-}Silva and
Andreas G. Veneris},
title = {Automated Design Debugging With Maximum Satisfiability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1804--1817},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061270},
doi = {10.1109/TCAD.2010.2061270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenSMV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenW10,
author = {Yung{-}Chih Chen and
Chun{-}Yao Wang},
title = {Fast Node Merging With Don't Cares Using Logic Implications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1827--1832},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2058510},
doi = {10.1109/TCAD.2010.2058510},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenX10,
author = {Zhen Chen and
Dong Xiang},
title = {A Novel Test Application Scheme for High Transition Fault Coverage
and Low Test Cost},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {966--976},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048359},
doi = {10.1109/TCAD.2010.2048359},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenX10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiouCJC10,
author = {De{-}Shiuan Chiou and
Yu{-}Ting Chen and
Da{-}Cheng Juan and
Shih{-}Chieh Chang},
title = {Sleep Transistor Sizing for Leakage Power Minimization Considering
Temporal Correlation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1285--1289},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2046812},
doi = {10.1109/TCAD.2010.2046812},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChiouCJC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiKDR10,
author = {Seung Hoon Choi and
Kunhyuk Kang and
Florentin Dartu and
Kaushik Roy},
title = {Timed Input Pattern Generation for an Accurate Delay Calculation Under
Multiple Input Switching},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {497--502},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035482},
doi = {10.1109/TCAD.2009.2035482},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiKDR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouCK10,
author = {Hong{-}Zu Chou and
Kai{-}Hui Chang and
Sy{-}Yen Kuo},
title = {Accurately Handle Don't-Care Conditions in High-Level Designs and
Application for Reducing Initialized Registers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {646--651},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042905},
doi = {10.1109/TCAD.2010.2042905},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouCK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouM10,
author = {Chen{-}Ling Chou and
Radu Marculescu},
title = {Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor
Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {78--91},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034348},
doi = {10.1109/TCAD.2009.2034348},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouM10a,
author = {Chen{-}Ling Chou and
Radu Marculescu},
title = {Designing Heterogeneous Embedded Network-on-Chip Platforms With Users
in Mind},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1301--1314},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049045},
doi = {10.1109/TCAD.2010.2049045},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouM10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChunO10,
author = {Sunghoon Chun and
Alex Orailoglu},
title = {DiSC: {A} New Diagnosis Method for Multiple Scan Chain Failures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {2051--2055},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061110},
doi = {10.1109/TCAD.2010.2061110},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChunO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungH10,
author = {Eric S. Chung and
James C. Hoe},
title = {High-Level Design and Validation of the BlueSPARC Multithreaded Processor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1459--1470},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2057870},
doi = {10.1109/TCAD.2010.2057870},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ConcerBSLC10,
author = {Nicola Concer and
Luciano Bononi and
Michael Soulie and
Riccardo Locatelli and
Luca P. Carloni},
title = {The Connection-Then-Credit Flow Control Protocol for Heterogeneous
Multicore Systems-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {869--882},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048592},
doi = {10.1109/TCAD.2010.2048592},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ConcerBSLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongGL10,
author = {Jason Cong and
Puneet Gupta and
John Lee},
title = {Evaluating Statistical Power Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1750--1762},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061390},
doi = {10.1109/TCAD.2010.2061390},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongGL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CzajkowskiB10,
author = {Tomasz S. Czajkowski and
Stephen Dean Brown},
title = {Decomposition-Based Vectorless Toggle Rate Computation for {FPGA}
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1723--1735},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061250},
doi = {10.1109/TCAD.2010.2061250},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CzajkowskiB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CzyszMMRT10,
author = {Dariusz Czysz and
Grzegorz Mrugalski and
Nilanjan Mukherjee and
Janusz Rajski and
Jerzy Tyszer},
title = {On Compaction Utilizing Inter and Intra-Correlation of Unknown States},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {117--126},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035550},
doi = {10.1109/TCAD.2009.2035550},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CzyszMMRT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasKKJZ10,
author = {Debasish Das and
Kip Killpack and
Chandramouli V. Kashyap and
Abhijit Jas and
Hai Zhou},
title = {Pessimism Reduction in Coupling-Aware Static Timing Analysis Using
Timing and Logic Filtering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {466--478},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035532},
doi = {10.1109/TCAD.2009.2035532},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasKKJZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasS10,
author = {Sukanta Das and
Biplab K. Sikdar},
title = {A Scalable Test Structure for Multicore Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {127--137},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034349},
doi = {10.1109/TCAD.2009.2034349},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DeySB10,
author = {Soumyajit Dey and
Dipankar Sarkar and
Anupam Basu},
title = {A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1028--1041},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049067},
doi = {10.1109/TCAD.2010.2049067},
timestamp = {Mon, 08 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DeySB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DinhCW10,
author = {Quang Dinh and
Deming Chen and
Martin D. F. Wong},
title = {A Routing Approach to Reduce Glitches in Low Power FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {235--240},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035564},
doi = {10.1109/TCAD.2009.2035564},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DinhCW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DongZX10,
author = {Xiangyu Dong and
Jishen Zhao and
Yuan Xie},
title = {Fabrication Cost Analysis and Cost-Aware Design Space Exploration
for 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1959--1972},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2062811},
doi = {10.1109/TCAD.2010.2062811},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DongZX10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangC10,
author = {Jia{-}Wei Fang and
Yao{-}Wen Chang},
title = {Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering
Signal Skews},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {711--721},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043586},
doi = {10.1109/TCAD.2010.2043586},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FangC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FerrandiLPST10,
author = {Fabrizio Ferrandi and
Pier Luca Lanzi and
Christian Pilato and
Donatella Sciuto and
Antonino Tumeo},
title = {Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications
on Heterogeneous Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {911--924},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048354},
doi = {10.1109/TCAD.2010.2048354},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FerrandiLPST10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FerzliCN10,
author = {Imad A. Ferzli and
Eli Chiprout and
Farid N. Najm},
title = {Verification and Codesign of the Package and Die Power Delivery System
Using Wavelets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {92--102},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034563},
doi = {10.1109/TCAD.2009.2034563},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FerzliCN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GandikotaCBS10,
author = {Ravikishore Gandikota and
Kaviraj Chopra and
David T. Blaauw and
Dennis Sylvester},
title = {Victim Alignment in Crosstalk-Aware Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {261--274},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035484},
doi = {10.1109/TCAD.2009.2035484},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GandikotaCBS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaneshpureK10,
author = {Kunal P. Ganeshpure and
Sandip Kundu},
title = {On {ATPG} for Multiple Aggressor Crosstalk Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {774--787},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043589},
doi = {10.1109/TCAD.2010.2043589},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaneshpureK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaJK10,
author = {Mohit Gupta and
Kwangok Jeong and
Andrew B. Kahng},
title = {Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation
for Bimodal {CD} Distribution in Double Patterning Lithography},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1229--1242},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049041},
doi = {10.1109/TCAD.2010.2049041},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaJK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuzeyWLF10,
author = {Onur Guzey and
Li{-}C. Wang and
Jeremy R. Levitt and
Harry Foster},
title = {Increasing the Efficiency of Simulation-Based Functional Verification
Through Unsupervised Support Vector Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {138--148},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034347},
doi = {10.1109/TCAD.2009.2034347},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuzeyWLF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanSJ10,
author = {HyoJung Han and
Fabio Somenzi and
HoonSang Jin},
title = {Making Deduction More Effective in {SAT} Solvers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1271--1284},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049135},
doi = {10.1109/TCAD.2010.2049135},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanSJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HashemiG10,
author = {Matin Hashemi and
Soheil Ghiasi},
title = {Versatile Task Assignment for Heterogeneous Soft Dual-Processor Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {414--425},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041856},
doi = {10.1109/TCAD.2010.2041856},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HashemiG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoCFC10,
author = {Kuan{-}Hsien Ho and
Yen{-}Pin Chen and
Jia{-}Wei Fang and
Yao{-}Wen Chang},
title = {{ECO} Timing Optimization Using Spare Cells and Technology Remapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {697--710},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043573},
doi = {10.1109/TCAD.2010.2043573},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoCFC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiaoCW10,
author = {Yu{-}Ying Hsiao and
Chao{-}Hsun Chen and
Cheng{-}Wen Wu},
title = {Built-In Self-Repair Schemes for Flash Memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1243--1256},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049051},
doi = {10.1109/TCAD.2010.2049051},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiaoCW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehCLH10,
author = {Wen{-}Wen Hsieh and
Shih{-}Liang Chen and
I{-}Sheng Lin and
TingTing Hwang},
title = {A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in
At-Speed Scan Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {289--298},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035584},
doi = {10.1109/TCAD.2009.2035584},
timestamp = {Fri, 09 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehCLH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsuCC10,
author = {Chin{-}Hsiung Hsu and
Huang{-}Yu Chen and
Yao{-}Wen Chang},
title = {Multilayer Global Routing With Via and Wire Capacity Considerations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {685--696},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043575},
doi = {10.1109/TCAD.2010.2043575},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsuCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangKHSJI10,
author = {Zhangcai Huang and
Atsushi Kurokawa and
Masanori Hashimoto and
Takashi Sato and
Minglu Jiang and
Yasuaki Inoue},
title = {Modeling the Overshooting Effect for {CMOS} Inverter Delay Analysis
in Nanometer Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {250--260},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035539},
doi = {10.1109/TCAD.2009.2035539},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangKHSJI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLH10,
author = {Tsung{-}Wei Huang and
Chun{-}Hsien Lin and
Tsung{-}Yi Ho},
title = {A Contamination Aware Droplet Routing Algorithm for the Synthesis
of Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1682--1695},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2062770},
doi = {10.1109/TCAD.2010.2062770},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangX10,
author = {Lin Huang and
Qiang Xu},
title = {Economic Analysis of Testing Homogeneous Manycore Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1257--1270},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049052},
doi = {10.1109/TCAD.2010.2049052},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuangX10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JafariLJY10,
author = {Fahimeh Jafari and
Zhonghai Lu and
Axel Jantsch and
Mohammad Hossien Yaghmaee},
title = {Buffer Optimization in Network-on-Chip Through Flow Regulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1973--1986},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2063130},
doi = {10.1109/TCAD.2010.2063130},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JafariLJY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JaffariA10,
author = {Javid Jaffari and
Mohab Anis},
title = {Advanced Variance Reduction and Sampling Techniques for Efficient
Statistical Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1894--1907},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061553},
doi = {10.1109/TCAD.2010.2061553},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JaffariA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JangKK10,
author = {Yongho Jang and
Jungsoo Kim and
Chong{-}Min Kyung},
title = {Topology Synthesis for Low Power Cascaded Crossbar Switches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {2041--2045},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2072730},
doi = {10.1109/TCAD.2010.2072730},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JangKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JangP10,
author = {Wooyoung Jang and
David Z. Pan},
title = {An SDRAM-Aware Router for Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1572--1585},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061251},
doi = {10.1109/TCAD.2010.2061251},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JangP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JavaidIP10,
author = {Haris Javaid and
Aleksandar Ignjatovic and
Sri Parameswaran},
title = {Rapid Design Space Exploration of Application Specific Heterogeneous
Pipelined Multiprocessor Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1777--1789},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061353},
doi = {10.1109/TCAD.2010.2061353},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JavaidIP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JeongKPY10,
author = {Kwangok Jeong and
Andrew B. Kahng and
Chul{-}Hong Park and
Hailong Yao},
title = {Dose Map and Placement Co-Optimization for Improved Timing Yield and
Leakage Power},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1070--1082},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048397},
doi = {10.1109/TCAD.2010.2048397},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JeongKPY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JeongLHLK10,
author = {Woosik Jeong and
Joohwan Lee and
Taewoo Han and
Kaangchil Lee and
Sungho Kang},
title = {An Advanced {BIRA} for Memories With an Optimal Repair Rate and Fast
Analysis Speed by Using a Branch Analyzer},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {2014--2026},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2062830},
doi = {10.1109/TCAD.2010.2062830},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JeongLHLK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JhaveriRLPSH10,
author = {Tejas Jhaveri and
Vyacheslav Rovner and
Lars Liebmann and
Larry T. Pileggi and
Andrzej J. Strojwas and
Jason Hibbeler},
title = {Co-Optimization of Circuits, Layout and Lithography for Predictive
Technology Scaling Beyond Gratings},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {509--527},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042882},
doi = {10.1109/TCAD.2010.2042882},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JhaveriRLPSH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JoshiCSBA10,
author = {Vivek Joshi and
Brian Cline and
Dennis Sylvester and
David T. Blaauw and
Kanak Agarwal},
title = {Mechanical Stress Aware Optimization for Leakage Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {722--736},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042893},
doi = {10.1109/TCAD.2010.2042893},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JoshiCSBA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungP10,
author = {Hwisung Jung and
Massoud Pedram},
title = {Supervised Learning Based Power Management for Multicore Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1395--1408},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2059270},
doi = {10.1109/TCAD.2010.2059270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngPXY10,
author = {Andrew B. Kahng and
Chul{-}Hong Park and
Xu Xu and
Hailong Yao},
title = {Layout Decomposition Approaches for Double Patterning Lithography},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {939--952},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048374},
doi = {10.1109/TCAD.2010.2048374},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngPXY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KangKYK10,
author = {Kyungsu Kang and
Jungsoo Kim and
Sungjoo Yoo and
Chong{-}Min Kyung},
title = {Temperature-Aware Integrated {DVFS} and Power Gating for Executing
Tasks With Runtime Distribution},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1381--1394},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2059290},
doi = {10.1109/TCAD.2010.2059290},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KangKYK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarfaSM10,
author = {Chandan Karfa and
Dipankar Sarkar and
Chitta Mandal},
title = {Verification of Datapath and Controller Generation Phase in High-Level
Synthesis of Digital Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {479--492},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035542},
doi = {10.1109/TCAD.2009.2035542},
timestamp = {Mon, 08 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KarfaSM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KengSV10,
author = {Brian Keng and
Sean Safarpour and
Andreas G. Veneris},
title = {Bounded Model Debugging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1790--1803},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061370},
doi = {10.1109/TCAD.2010.2061370},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KengSV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhursheedACH10,
author = {S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
Krishnendu Chakrabarty and
Peter Harrod},
title = {Gate-Sizing-Based Single V\({}_{\mbox{dd}}\) Test for Bridge Defects
in Multivoltage Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1409--1421},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2059310},
doi = {10.1109/TCAD.2010.2059310},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KhursheedACH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimL10,
author = {Taemin Kim and
Xun Liu},
title = {A Functional Unit and Register Binding Algorithm for Interconnect
Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {641--646},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042903},
doi = {10.1109/TCAD.2010.2042903},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimVY10,
author = {Jintae Kim and
Lieven Vandenberghe and
Chih{-}Kong Ken Yang},
title = {Convex Piecewise-Linear Modeling Method for Circuit Optimization via
Geometric Programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1823--1827},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2053151},
doi = {10.1109/TCAD.2010.2053151},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimVY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KinsmanN10,
author = {Adam B. Kinsman and
Nicola Nicolici},
title = {Bit-Width Allocation for Hardware Accelerators for Scientific Computing
Using SAT-Modulo Theory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {405--413},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041839},
doi = {10.1109/TCAD.2010.2041839},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KinsmanN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KohlerSR10,
author = {Ad{\'{a}}n Kohler and
Gert Schley and
Martin Radetzki},
title = {Fault Tolerant Network on Chip Switching With Graceful Performance
Degradation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {883--896},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048399},
doi = {10.1109/TCAD.2010.2048399},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KohlerSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarA10,
author = {Akhilesh Kumar and
Mohab Anis},
title = {IR-Drop Management in FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {988--993},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043593},
doi = {10.1109/TCAD.2010.2043593},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarMCH10,
author = {Akash Kumar and
Bart Mesman and
Henk Corporaal and
Yajun Ha},
title = {Iterative Probabilistic Performance Prediction for Multi-Application
Multiprocessor Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {538--551},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042887},
doi = {10.1109/TCAD.2010.2042887},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarMCH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KunduLG10,
author = {Sudipta Kundu and
Sorin Lerner and
Rajesh K. Gupta},
title = {Translation Validation of High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {566--579},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042889},
doi = {10.1109/TCAD.2010.2042889},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KunduLG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeLW10,
author = {Kuang{-}Yao Lee and
Shing{-}Tung Lin and
Ting{-}Chi Wang},
title = {Enhanced Double Via Insertion Using Wire Bending},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {171--184},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035559},
doi = {10.1109/TCAD.2009.2035559},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeLW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeePS10,
author = {Hyein Lee and
Seungwhun Paik and
Youngsoo Shin},
title = {Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential
Circuits Based on Pulsed Latches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {355--366},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041845},
doi = {10.1109/TCAD.2010.2041845},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeePS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeS10,
author = {Jongeun Lee and
Aviral Shrivastava},
title = {A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction
for Register Files},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1018--1027},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049050},
doi = {10.1109/TCAD.2010.2049050},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeWKC10,
author = {Kuang{-}Yao Lee and
Ting{-}Chi Wang and
Cheng{-}Kok Koh and
Kai{-}Yuan Chao},
title = {Optimal Double Via Insertion With On-Track Preference},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {318--323},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035581},
doi = {10.1109/TCAD.2009.2035581},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeWKC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LefteriuA10,
author = {Sandra Lefteriu and
Athanasios C. Antoulas},
title = {A New Approach to Modeling Multiport Systems From Frequency-Domain
Data},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {14--27},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034500},
doi = {10.1109/TCAD.2009.2034500},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LefteriuA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Li10,
author = {Katherine Shu{-}Min Li},
title = {Multiple Scan Trees Synthesis for Test Time/Data and Routing Length
Reduction Under Output Constraint},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {618--626},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042896},
doi = {10.1109/TCAD.2010.2042896},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Li10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Li10a,
author = {Xin Li},
title = {Finding Deterministic Solution From Underdetermined Equation: Large-Scale
Performance Variability Modeling of Analog/RF Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1661--1668},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061292},
doi = {10.1109/TCAD.2010.2061292},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Li10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiHH10,
author = {Jin{-}Fu Li and
Yu{-}Jen Huang and
Yong{-}Jyun Hu},
title = {Testing Random Defect and Process Variation Induced Comparison Faults
of TCAMs With Asymmetric Cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1843--1847},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2072710},
doi = {10.1109/TCAD.2010.2072710},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiHH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiMWCVG10,
author = {Xin Li and
Colin C. McAndrew and
Weimin Wu and
Samir Chaudhry and
James Victory and
Gennady Gildenblat},
title = {Statistical Modeling With the {PSP} {MOSFET} Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {599--606},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042892},
doi = {10.1109/TCAD.2010.2042892},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiMWCVG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinC10,
author = {Cliff Chiung{-}Yu Lin and
Yao{-}Wen Chang},
title = {ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1315--1327},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049157},
doi = {10.1109/TCAD.2010.2049157},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinMM10,
author = {Yi{-}Wei Lin and
Malgorzata Marek{-}Sadowska and
Wojciech Maly},
title = {Layout Generator for Transistor-Level High-Density Regular Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {197--210},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035580},
doi = {10.1109/TCAD.2009.2035580},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinW10,
author = {Mingjie Lin and
John Wawrzynek},
title = {Improving {FPGA} Placement With Dynamically Adaptive Stochastic Tunneling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1858--1869},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061670},
doi = {10.1109/TCAD.2010.2061670},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinWG10,
author = {Mingjie Lin and
John Wawrzynek and
Abbas El Gamal},
title = {Exploring {FPGA} Routing Architecture Stochastically},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1509--1522},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061530},
doi = {10.1109/TCAD.2010.2061530},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinWG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuH10,
author = {Yifang Liu and
Jiang Hu},
title = {A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage
Assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {223--234},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035575},
doi = {10.1109/TCAD.2009.2035575},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuS10,
author = {Qunzeng Liu and
Sachin S. Sapatnekar},
title = {Capturing Post-Silicon Variations Using a Representative Critical
Path},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {211--222},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035552},
doi = {10.1109/TCAD.2009.2035552},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuSTC10,
author = {Feng Liu and
Xiaoyu Song and
Qingping Tan and
Gang Chen},
title = {Formal Analysis of End-Around-Carry Adder in Floating-Point Unit},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1655--1659},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2052391},
doi = {10.1109/TCAD.2010.2052391},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuSTC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuTCC10,
author = {Jui{-}Hsiang Liu and
Ming{-}Feng Tsai and
Lumdo Chen and
Charlie Chung{-}Ping Chen},
title = {Accurate and Analytical Statistical Spatial Correlation Modeling Based
on Singular Value Decomposition for {VLSI} {DFM} Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {580--589},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042890},
doi = {10.1109/TCAD.2010.2042890},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuTCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LoHDW10,
author = {Chih{-}Yen Lo and
Yu{-}Tsao Hsing and
Li{-}Ming Denq and
Cheng{-}Wen Wu},
title = {{SOC} Test Architecture and Method for 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1645--1649},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2051732},
doi = {10.1109/TCAD.2010.2051732},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LoHDW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuCLC10,
author = {Chien Pang Lu and
Mango Chia{-}Tso Chao and
Chen Hsing Lo and
Chih{-}Wei Chang},
title = {A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {240--245},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2040011},
doi = {10.1109/TCAD.2009.2040011},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuCLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuZSZ10,
author = {Yinghai Lu and
Hai Zhou and
Li Shang and
Xuan Zeng},
title = {Multicore Parallelization of Min-Cost Flow for {CAD} Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1546--1557},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061150},
doi = {10.1109/TCAD.2010.2061150},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuZSZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LucasDC10,
author = {Gregory Lucas and
Chen Dong and
Deming Chen},
title = {Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis
for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1818--1822},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2056411},
doi = {10.1109/TCAD.2010.2056411},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LucasDC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Maffezzoni10,
author = {Paolo Maffezzoni},
title = {Computing the Synchronization Regions of Injection-Locked Strongly
Nonlinear Oscillators for Frequency Division Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1849--1857},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061450},
doi = {10.1109/TCAD.2010.2061450},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Maffezzoni10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaheshV10,
author = {Raveendranatha P. Mahesh and
A. Prasad Vinod},
title = {New Reconfigurable Architectures for Implementing {FIR} Filters With
Low Complexity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {275--288},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035548},
doi = {10.1109/TCAD.2009.2035548},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaheshV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaideeB10,
author = {Pongstorn Maidee and
Kia Bazargan},
title = {Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for
LUT-Based Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1870--1883},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061750},
doi = {10.1109/TCAD.2010.2061750},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaideeB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MajzoubSWW10,
author = {Sohaib Majzoub and
Resve A. Saleh and
Steven J. E. Wilton and
Rabab K. Ward},
title = {Energy Optimization for Many-Core Platforms: Communication and {PVT}
Aware Voltage-Island Formation and Voltage Selection Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {816--829},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043587},
doi = {10.1109/TCAD.2010.2043587},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MajzoubSWW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarculescuJ10,
author = {Radu Marculescu and
Axel Jantsch},
title = {Guest Editorial: Special Section on the {ACM/IEEE} Symposium on Networks-on-Chip
2009},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {853--854},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048595},
doi = {10.1109/TCAD.2010.2048595},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarculescuJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaricauG10,
author = {Elie Maricau and
Georges G. E. Gielen},
title = {Efficient Variability-Aware {NBTI} and Hot Carrier Circuit Reliability
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1884--1893},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2062870},
doi = {10.1109/TCAD.2010.2062870},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaricauG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MerajiZT10,
author = {Sina Meraji and
Wei Zhang and
Carl Tropper},
title = {On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level
Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1368--1380},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049044},
doi = {10.1109/TCAD.2010.2049044},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MerajiZT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MeterelliyozKR10,
author = {Mesut Meterelliyoz and
Jaydeep P. Kulkarni and
Kaushik Roy},
title = {Analysis of {SRAM} and eDRAM Cache Memories Under Spatial Temperature
Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {2--13},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035535},
doi = {10.1109/TCAD.2009.2035535},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MeterelliyozKR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Miskov-ZivanovM10,
author = {Natasa Miskov{-}Zivanov and
Diana Marculescu},
title = {Multiple Transient Faults in Combinational and Sequential Circuits:
{A} Systematic Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1614--1627},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061131},
doi = {10.1109/TCAD.2010.2061131},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Miskov-ZivanovM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ModarressiTS10,
author = {Mehdi Modarressi and
Arash Tavakkol and
Hamid Sarbazi{-}Azad},
title = {Virtual Point-to-Point Connections for NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {855--868},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048402},
doi = {10.1109/TCAD.2010.2048402},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ModarressiTS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoiseevKW10,
author = {Konstantin Moiseev and
Avinoam Kolodny and
Shmuel Wimer},
title = {Interconnect Bundle Sizing Under Discrete Design Rules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1650--1654},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2051633},
doi = {10.1109/TCAD.2010.2051633},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoiseevKW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Morin-AlloryBBZ10,
author = {Katell Morin{-}Allory and
Marc Boule and
Dominique Borrione and
Zeljko Zilic},
title = {Validating Assertion Language Rewrite Rules and Semantics With Automated
Theorem Provers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1436--1448},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049150},
doi = {10.1109/TCAD.2010.2049150},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Morin-AlloryBBZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeePRT10,
author = {Nilanjan Mukherjee and
Artur Pogiel and
Janusz Rajski and
Jerzy Tyszer},
title = {High Volume Diagnosis in Memory {BIST} Based on Compressed Failure
Data},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {441--453},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041852},
doi = {10.1109/TCAD.2010.2041852},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeePRT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Musoll10,
author = {Enric Musoll},
title = {Hardware-Based Load Balancing for Massive Multicore Architectures
Implementing Power Gating},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {493--497},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2018863},
doi = {10.1109/TCAD.2009.2018863},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Musoll10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NamS10,
author = {Gi{-}Joon Nam and
Prashant Saxena},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {169--170},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2037283},
doi = {10.1109/TCAD.2009.2037283},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NamS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NoccoQ10,
author = {Sergio Nocco and
Stefano Quer},
title = {A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling
Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {2027--2040},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061631},
doi = {10.1109/TCAD.2010.2061631},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NoccoQ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OgrasBM10,
author = {{\"{U}}mit Y. Ogras and
Paul Bogdan and
Radu Marculescu},
title = {An Analytical Approach for Network-on-Chip Performance Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {2001--2013},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061613},
doi = {10.1109/TCAD.2010.2061613},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/OgrasBM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaikSKS10,
author = {Seungwhun Paik and
Insup Shin and
Taewhan Kim and
Youngsoo Shin},
title = {HLS-l: {A} High-Level Synthesis Framework for Latch-Based Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {657--670},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043588},
doi = {10.1109/TCAD.2010.2043588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaikSKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PalesiKC10,
author = {Maurizio Palesi and
Shashi Kumar and
Vincenzo Catania},
title = {Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance
in Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {426--440},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041851},
doi = {10.1109/TCAD.2010.2041851},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PalesiKC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PangRZ10,
author = {Yu Pang and
Katarzyna Radecka and
Zeljko Zilic},
title = {Optimization of Imprecise Circuits Represented by Taylor Series and
Real-Valued Polynomials},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1177--1190},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049154},
doi = {10.1109/TCAD.2010.2049154},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PangRZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{TOV:} Sequential Test Generation by Ordering of Test Vectors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {454--465},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041985},
doi = {10.1109/TCAD.2010.2041985},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Test Generation With Test Vector Improvement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {502--506},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041853},
doi = {10.1109/TCAD.2010.2041853},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Clustering of Undetectable Single Stuck-At Faults and Test Quality
in Full-Scan Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1135--1140},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2046448},
doi = {10.1109/TCAD.2010.2046448},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Hazard-Based Detection Conditions for Improved Transition Path Delay
Fault Coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1449--1453},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049462},
doi = {10.1109/TCAD.2010.2049462},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10d,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Undetectable Faults and Fault Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1832--1837},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2053476},
doi = {10.1109/TCAD.2010.2053476},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QianLD10,
author = {Yue Qian and
Zhonghai Lu and
Wenhua Dou},
title = {Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {802--815},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043572},
doi = {10.1109/TCAD.2010.2043572},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QianLD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RajaramP10,
author = {Anand Rajaram and
David Z. Pan},
title = {MeshWorks: {A} Comprehensive Framework for Optimized Clock Mesh Network
Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1945--1958},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061130},
doi = {10.1109/TCAD.2010.2061130},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RajaramP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RakC10,
author = {{\'{A}}d{\'{a}}m R{\'{a}}k and
Gy{\"{o}}rgy Cserey},
title = {Macromodeling of the Memristor in {SPICE}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {632--636},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042900},
doi = {10.1109/TCAD.2010.2042900},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RakC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ReisS10,
author = {Timo Reis and
Tatjana Stykel},
title = {{PABTEC:} Passivity-Preserving Balanced Truncation for Electrical
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1354--1367},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2059330},
doi = {10.1109/TCAD.2010.2059330},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ReisS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RommesS10,
author = {Joost Rommes and
Wil H. A. Schilders},
title = {Efficient Methods for Large Resistor Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {28--39},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034402},
doi = {10.1109/TCAD.2009.2034402},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RommesS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyBC10,
author = {Sudip Roy and
Bhargab B. Bhattacharya and
Krishnendu Chakrabarty},
title = {Optimization of Dilution and Mixing of Biochemical Samples Using Digital
Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1696--1708},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061790},
doi = {10.1109/TCAD.2010.2061790},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RoyBC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar10,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {1},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2037282},
doi = {10.1109/TCAD.2009.2037282},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchaferW10,
author = {Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Kazutoshi Wakabayashi},
title = {Design Space Exploration Acceleration Through Operation Clustering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {153--157},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035579},
doi = {10.1109/TCAD.2009.2035579},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchaferW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeiculescuMBM10,
author = {Ciprian Seiculescu and
Srinivasan Murali and
Luca Benini and
Giovanni De Micheli},
title = {SunFloor 3D: {A} Tool for Networks on Chip Topology Synthesis for
3-D Systems on Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1987--2000},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061610},
doi = {10.1109/TCAD.2010.2061610},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeiculescuMBM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SharifiR10,
author = {Shervin Sharifi and
Tajana Simunic Rosing},
title = {Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient
Dynamic Thermal Management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1586--1599},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061310},
doi = {10.1109/TCAD.2010.2061310},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SharifiR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Shelar10,
author = {Rupesh S. Shelar},
title = {Routing With Constraints for Post-Grid Clock Distribution in Microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {245--249},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2040012},
doi = {10.1109/TCAD.2009.2040012},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Shelar10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShenQWXZL10,
author = {ShengYu Shen and
Ying Qin and
Kefei Wang and
Liquan Xiao and
Jianmin Zhang and
Sikun Li},
title = {Synthesizing Complementary Circuits Automatically},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1191--1202},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049152},
doi = {10.1109/TCAD.2010.2049152},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShenQWXZL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiTYO10,
author = {Youhua Shi and
Nozomu Togawa and
Masao Yanagisawa and
Tatsuo Ohtsuki},
title = {Improved Launch for Higher {TDF} Coverage With Fewer Test Patterns},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1294--1299},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2047475},
doi = {10.1109/TCAD.2010.2047475},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShiTYO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinKK10,
author = {Sangho Shin and
Kyungmin Kim and
Sung{-}Mo Kang},
title = {Compact Models for Memristors Based on Charge-Flux Constitutive Relationships},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {590--598},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042891},
doi = {10.1109/TCAD.2010.2042891},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShinKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SilvaPS10,
author = {Lu{\'{\i}}s Guerra e Silva and
Joel R. Phillips and
Lu{\'{\i}}s Miguel Silveira},
title = {Effective Corner-Based Techniques for Variation-Aware {IC} Timing
Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {157--162},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034343},
doi = {10.1109/TCAD.2009.2034343},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SilvaPS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SilvaPS10a,
author = {Jo{\~{a}}o M. S. Silva and
Joel R. Phillips and
Lu{\'{\i}}s Miguel Silveira},
title = {Efficient Simulation of Power Grids},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1523--1532},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061512},
doi = {10.1109/TCAD.2010.2061512},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SilvaPS10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SingheeR10,
author = {Amith Singhee and
Rob A. Rutenbar},
title = {Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube
Sampling for Statistical Circuit Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1763--1776},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2062750},
doi = {10.1109/TCAD.2010.2062750},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SingheeR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SmithCC10,
author = {Alastair M. Smith and
George A. Constantinides and
Peter Y. K. Cheung},
title = {{FPGA} Architecture Optimization Using Geometric Programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1163--1176},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049046},
doi = {10.1109/TCAD.2010.2049046},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SmithCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SoveikoNA10,
author = {Nick Soveiko and
Michel S. Nakhla and
Ramachandra Achar},
title = {Comparison Study of Performance of Parallel Steady State Solver on
Different Computer Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {65--77},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034499},
doi = {10.1109/TCAD.2009.2034499},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SoveikoNA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrivastavaXSB10,
author = {Navin Srivastava and
Chuan Xu and
Roberto Suaya and
Kaustav Banerjee},
title = {Corrections to "Analytical Expressions for High-Frequency {VLSI} Interconnect
Impedance Extraction in the Presence of a Multilayer Conductive Substrate"
[Jul 09 1047-1060]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {849},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2047753},
doi = {10.1109/TCAD.2010.2047753},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SrivastavaXSB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuHYCC10,
author = {Yu{-}Shih Su and
Wing{-}Kai Hon and
Cheng{-}Chih Yang and
Shih{-}Chieh Chang and
Yeong{-}Jar Chang},
title = {Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable
Delay Buffers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1921--1930},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061654},
doi = {10.1109/TCAD.2010.2061654},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuHYCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuissaRDHG10,
author = {Abraham Suissa and
Olivier Romain and
Julien Denoulet and
Khalil Hachicha and
Patrick Garda},
title = {Empirical Method Based on Neural Networks for Analog Power Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {839--844},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043759},
doi = {10.1109/TCAD.2010.2043759},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuissaRDHG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuvakD10,
author = {Onder Suvak and
Alper Demir},
title = {Quadratic Approximations for the Isochrons of Oscillators: {A} General
Theory, Advanced Numerical Methods, and Accurate Phase Computations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1215--1228},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049056},
doi = {10.1109/TCAD.2010.2049056},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuvakD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TannirK10,
author = {Dani Tannir and
Roni Khazaka},
title = {Computation of Intermodulation Distortion in {RF} Circuits Using Single-Tone
Moments Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1121--1125},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2044672},
doi = {10.1109/TCAD.2010.2044672},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TannirK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TehHT10,
author = {Siew{-}Hong Teh and
Chun{-}Huat Heng and
Arthur Tay},
title = {Performance-Based Optical Proximity Correction Methodology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {51--64},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2032360},
doi = {10.1109/TCAD.2009.2032360},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TehHT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TenentesKK10,
author = {Vasileios Tenentes and
Xrysovalantis Kavousianos and
Emmanouil Kalligeros},
title = {Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test
Data Compression and Test Set Embedding for {IP} Cores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1640--1644},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2051096},
doi = {10.1109/TCAD.2010.2051096},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TenentesKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThakkerSBP10,
author = {Rajesh Amratlal Thakker and
Chaitanya Sathe and
Maryam Shojaei Baghini and
Mahesh B. Patil},
title = {A Table-Based Approach to Study the Impact of Process Variations on
FinFET Circuit Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {627--631},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042899},
doi = {10.1109/TCAD.2010.2042899},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ThakkerSBP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TilleED10,
author = {Daniel Tille and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Incremental Solving Techniques for SAT-based {ATPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1125--1130},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2044673},
doi = {10.1109/TCAD.2010.2044673},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TilleED10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TongC10,
author = {Yang{-}Shan Tong and
Sao{-}Jie Chen},
title = {An Automatic Optical Simulation-Based Lithography Hotspot Fix Flow
for Post-Route Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {671--684},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043756},
doi = {10.1109/TCAD.2010.2043756},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TongC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TranTB10,
author = {Anh Thien Tran and
Dean Nguyen Truong and
Bevan M. Baas},
title = {A Reconfigurable Source-Synchronous On-Chip Network for {GALS} Many-Core
Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {897--910},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048594},
doi = {10.1109/TCAD.2010.2048594},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TranTB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsengHL10,
author = {Tsu{-}Wei Tseng and
Yu{-}Jen Huang and
Jin{-}Fu Li},
title = {{DABISR:} {A} Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port
RAMs in SoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1628--1639},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061570},
doi = {10.1109/TCAD.2010.2061570},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsengHL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TzengH10,
author = {Chao{-}Wen Tzeng and
Shi{-}Yu Huang},
title = {Split-Masking: An Output Masking Scheme for Effective Compound Defect
Diagnosis in Scan Architecture With Test Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {834--839},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043758},
doi = {10.1109/TCAD.2010.2043758},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TzengH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VasudevanE10,
author = {Nalini Vasudevan and
Stephen A. Edwards},
title = {Buffer Sharing in Rendezvous Programs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1471--1480},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2052840},
doi = {10.1109/TCAD.2010.2052840},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/VasudevanE10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VermaBI10,
author = {Ajay Kumar Verma and
Philip Brisk and
Paolo Ienne},
title = {Fast, Nearly Optimal {ISE} Identification With {I/O} Serialization
Through Maximal Clique Enumeration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {341--354},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041849},
doi = {10.1109/TCAD.2010.2041849},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VermaBI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VillenaS10,
author = {Jorge Fernandez Villena and
Lu{\'{\i}}s Miguel Silveira},
title = {{SPARE} - {A} Scalable Algorithm for Passive, Structure Preserving,
Parameter-Aware Model Order Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {925--938},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048372},
doi = {10.1109/TCAD.2010.2048372},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VillenaS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ViraraghavanAV10,
author = {Janakiraman Viraraghavan and
Bharadwaj Amrutur and
V. Visvanathan},
title = {Voltage and Temperature Aware Statistical Leakage Analysis Framework
Using Artificial Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1056--1069},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049059},
doi = {10.1109/TCAD.2010.2049059},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ViraraghavanAV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangSRC10,
author = {Jiajing Wang and
Amith Singhee and
Rob A. Rutenbar and
Benton H. Calhoun},
title = {Two Fast Methods for Estimating the Minimum Standby Supply Voltage
for Large SRAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {12},
pages = {1908--1920},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061810},
doi = {10.1109/TCAD.2010.2061810},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangSRC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangWWFCSGJ10,
author = {Laung{-}Terng Wang and
Xiaoqing Wen and
Shianling Wu and
Hiroshi Furukawa and
Hao{-}Jan Chao and
Boryau Sheu and
Jianghao Guo and
Wen{-}Ben Jone},
title = {Using Launch-on-Capture for Testing {BIST} Designs Containing Synchronous
and Asynchronous Clock Domains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {299--312},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035483},
doi = {10.1109/TCAD.2009.2035483},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangWWFCSGJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuLK10,
author = {Chin{-}Hsien Wu and
Hsin{-}Hung Lin and
Tei{-}Wei Kuo},
title = {An Adaptive Flash Translation Layer for High-Performance Storage Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {953--965},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048362},
doi = {10.1109/TCAD.2010.2048362},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuLK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiaBW10,
author = {Likun Xia and
Ian M. Bell and
Antony J. Wilkinson},
title = {Automated Model Generation Algorithm for High-Level Fault Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1140--1145},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2045556},
doi = {10.1109/TCAD.2010.2045556},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiaBW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuCP10,
author = {Tao Xu and
Krishnendu Chakrabarty and
Vamsee K. Pamula},
title = {Defect-Tolerant Design and Optimization of a Digital Microfluidic
Biochip for Protein Crystallization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {4},
pages = {552--565},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2042888},
doi = {10.1109/TCAD.2010.2042888},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XuCP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuL10,
author = {Xiaoxi Xu and
Cheng{-}Chew Lim},
title = {Modeling Interrupts for Software-Based System-on-Chip Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {993--997},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043873},
doi = {10.1109/TCAD.2010.2043873},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanC10,
author = {Jackey Z. Yan and
Chris Chu},
title = {DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning
Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {367--381},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041850},
doi = {10.1109/TCAD.2010.2041850},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangCKK10,
author = {Myung{-}Hoon Yang and
Hyungjun Cho and
Wooheon Kang and
Sungho Kang},
title = {{EOF:} Efficient Built-In Redundancy Analysis Methodology With Optimal
Repair Rate},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1130--1135},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2044846},
doi = {10.1109/TCAD.2010.2044846},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangCKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangKH10,
author = {Hoeseok Yang and
Sungchan Kim and
Soonhoi Ha},
title = {An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking
MPSoC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {10},
pages = {1600--1613},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2061552},
doi = {10.1109/TCAD.2010.2061552},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangKH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeLZPH10,
author = {Xiaoji Ye and
Peng Li and
Min Zhao and
Rajendran Panda and
Jiang Hu},
title = {Scalable Analysis of Mesh-Based Clock Distribution Networks Using
Application-Specific Reduced Order Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1342--1353},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2059090},
doi = {10.1109/TCAD.2010.2059090},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YeLZPH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YilmazCT10,
author = {Mahmut Yilmaz and
Krishnendu Chakrabarty and
Mohammad Tehranipoor},
title = {Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep
Submicrometer Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {760--773},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043591},
doi = {10.1109/TCAD.2010.2043591},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YilmazCT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuA10,
author = {Qiaoyan Yu and
Paul Ampadu},
title = {A Flexible Parallel Simulator for Networks-on-Chip With Error Control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {1},
pages = {103--116},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2034353},
doi = {10.1109/TCAD.2009.2034353},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuB10,
author = {Xiaochun Yu and
Ronald D. Blanton},
title = {Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary
Characteristics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {6},
pages = {977--987},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048352},
doi = {10.1109/TCAD.2010.2048352},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanYP10,
author = {Kun Yuan and
Jae{-}Seok Yang and
David Z. Pan},
title = {Double Patterning Layout Decomposition for Simultaneous Conflict and
Stitch Minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {2},
pages = {185--196},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2009.2035577},
doi = {10.1109/TCAD.2009.2035577},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuanYP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangW10,
author = {Zheng Zhang and
Ngai Wong},
title = {An Efficient Projector-Based Passivity Test for Descriptor Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {8},
pages = {1203--1214},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049048},
doi = {10.1109/TCAD.2010.2049048},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZolotovXFV10,
author = {Vladimir Zolotov and
Jinjun Xiong and
Hanif Fatemi and
Chandu Visweswariah},
title = {Statistical Path Selection for At-Speed Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {749--759},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043570},
doi = {10.1109/TCAD.2010.2043570},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZolotovXFV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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