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@article{DBLP:journals/tcad/AbdollahiP08,
author = {Afshin Abdollahi and
Massoud Pedram},
title = {Symmetry Detection and Boolean Matching Utilizing a Signature-Based
Canonical Form of Boolean Functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1128--1137},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923256},
doi = {10.1109/TCAD.2008.923256},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AbdollahiP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Abu-RahmaA08,
author = {Mohamed H. Abu{-}Rahma and
Mohab Anis},
title = {A Statistical Design-Oriented Delay Variation Model Accounting for
Within-Die Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1983--1995},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006096},
doi = {10.1109/TCAD.2008.2006096},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Abu-RahmaA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AcarO08,
author = {Erkan Acar and
Sule Ozev},
title = {Defect-Oriented Testing of {RF} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {920--931},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917578},
doi = {10.1109/TCAD.2008.917578},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcarO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgostaBS08,
author = {Giovanni Agosta and
Francesco Bruschi and
Donatella Sciuto},
title = {Static Analysis of Transaction-Level Communication Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1412--1424},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925791},
doi = {10.1109/TCAD.2008.925791},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgostaBS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AksoyCFM08,
author = {Levent Aksoy and
Eduardo A. C. da Costa and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
title = {Exact and Approximate Algorithms for the Optimization of Area and
Delay in Multiple Constant Multiplications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1013--1026},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923242},
doi = {10.1109/TCAD.2008.923242},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AksoyCFM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ArumiRF08,
author = {Daniel Arum{\'{\i}} and
Rosa Rodr{\'{\i}}guez{-}Monta{\~{n}}{\'{e}}s and
Joan Figueras},
title = {Experimental Characterization of {CMOS} Interconnect Open Defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {123--136},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907255},
doi = {10.1109/TCAD.2007.907255},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ArumiRF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AtasuODML08,
author = {Kubilay Atasu and
Can C. {\"{O}}zturan and
G{\"{u}}nhan D{\"{u}}ndar and
Oskar Mencer and
Wayne Luk},
title = {{CHIPS:} Custom Hardware Instruction Processor Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {528--541},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915536},
doi = {10.1109/TCAD.2008.915536},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AtasuODML08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BernardiSSSR08,
author = {Paolo Bernardi and
Ernesto S{\'{a}}nchez and
Massimiliano Schillaci and
Giovanni Squillero and
Matteo Sonza Reorda},
title = {An Effective Technique for the Automatic Generation of Diagnosis-Oriented
Programs for Processor Cores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {570--574},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915541},
doi = {10.1109/TCAD.2008.915541},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BernardiSSSR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BernasconiCDV08,
author = {Anna Bernasconi and
Valentina Ciriani and
Rolf Drechsler and
Tiziano Villa},
title = {Logic Minimization and Testability of 2-SPP Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1190--1202},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923072},
doi = {10.1109/TCAD.2008.923072},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BernasconiCDV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhardwajV08,
author = {Sarvesh Bhardwaj and
Sarma B. K. Vrudhula},
title = {Leakage Minimization of Digital Circuits Using Gate Sizing in the
Presence of Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {445--455},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.916341},
doi = {10.1109/TCAD.2008.916341},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhardwajV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhardwajVG08,
author = {Sarvesh Bhardwaj and
Sarma B. K. Vrudhula and
Amit Goel},
title = {A Unified Approach for Full Chip Statistical Timing and Leakage Analysis
of Nanoscale Circuits Considering Intradie Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1812--1825},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927671},
doi = {10.1109/TCAD.2008.927671},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhardwajVG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BlaauwCSS08,
author = {David T. Blaauw and
Kaviraj Chopra and
Ashish Srivastava and
Louis Scheffer},
title = {Statistical Timing Analysis: From Basic Principles to State of the
Art},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {589--607},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907047},
doi = {10.1109/TCAD.2007.907047},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BlaauwCSS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrennerSV08,
author = {Ulrich Brenner and
Markus Struzyna and
Jens Vygen},
title = {BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial
Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1607--1620},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927674},
doi = {10.1109/TCAD.2008.927674},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrennerSV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoJXHFHH08,
author = {Zhen Cao and
Tong Jing and
Jinjun Xiong and
Yu Hu and
Zhe Feng and
Lei He and
Xianlong Hong},
title = {Fashion: {A} Fast and Accurate Solution to Global Routing Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {726--737},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917590},
doi = {10.1109/TCAD.2008.917590},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CaoJXHFHH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CarmonaC08,
author = {Josep Carmona and
Jordi Cortadella},
title = {Encoding Large Asynchronous Controllers With {ILP} Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {20--33},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907238},
doi = {10.1109/TCAD.2007.907238},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CarmonaC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Castro-LopezGRF08,
author = {Rafael Castro{-}L{\'{o}}pez and
Oscar Guerra and
Elisenda Roca and
Francisco V. Fern{\'{a}}ndez},
title = {An Integrated Layout-Synthesis Approach for Analog ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1179--1189},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923417},
doi = {10.1109/TCAD.2008.923417},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Castro-LopezGRF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChandraiahD08,
author = {Pramod Chandraiah and
Rainer D{\"{o}}mer},
title = {Code and Data Structure Partitioning for Parallel and Flexible MPSoC
Specification Using Designer-Controlled Recoding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1078--1090},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923244},
doi = {10.1109/TCAD.2008.923244},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChandraiahD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangMB08,
author = {Kai{-}Hui Chang and
Igor L. Markov and
Valeria Bertacco},
title = {Fixing Design Errors With Counterexamples and Resynthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {184--188},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907257},
doi = {10.1109/TCAD.2007.907257},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangMB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChathakSK08,
author = {Karam S. Chatha and
Krishnan Srinivasan and
Goran Konjevod},
title = {Automated Techniques for Synthesis of Application-Specific Network-on-Chip
Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1425--1438},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925775},
doi = {10.1109/TCAD.2008.925775},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChathakSK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCC08,
author = {Tung{-}Chieh Chen and
Yi{-}Lin Chuang and
Yao{-}Wen Chang},
title = {Effective Wire Models for X-Architecture Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {654--658},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917959},
doi = {10.1109/TCAD.2008.917959},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCCCH08,
author = {Huang{-}Yu Chen and
Mei{-}Fang Chiang and
Yao{-}Wen Chang and
Lumdo Chen and
Brian Han},
title = {Full-Chip Routing Considering Double-Via Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {844--857},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917597},
doi = {10.1109/TCAD.2008.917597},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCCCH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCL08,
author = {Tung{-}Chieh Chen and
Yao{-}Wen Chang and
Shyh{-}Chang Lin},
title = {A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {286--294},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907065},
doi = {10.1109/TCAD.2007.907065},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCPC08,
author = {Tung{-}Chieh Chen and
Minsik Cho and
David Z. Pan and
Yao{-}Wen Chang},
title = {Metal-Density-Driven Placement for {CMP} Variation and Routability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2145--2155},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006148},
doi = {10.1109/TCAD.2008.2006148},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCPC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenJHCC08,
author = {Tung{-}Chieh Chen and
Zhe{-}Wei Jiang and
Tien{-}Chang Hsu and
Hsin{-}Chen Chen and
Yao{-}Wen Chang},
title = {NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs
With Preplaced Blocks and Density Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1228--1240},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923063},
doi = {10.1109/TCAD.2008.923063},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenJHCC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenSAGNY08,
author = {Changzhong Chen and
Dharmendra Saraswat and
Ramachandra Achar and
Emad Gad and
Michel S. Nakhla and
Mustapha Ch{\'{e}}rif{-}Eddine Yagoub},
title = {A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs
With {FD-PUL} Parameters Using Integrated Congruence Transform},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {574--578},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915535},
doi = {10.1109/TCAD.2008.915535},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenSAGNY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenW08,
author = {Yung{-}Chih Chen and
Chun{-}Yao Wang},
title = {An Implicit Approach to Minimizing Range-Equivalent Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1942--1955},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006088},
doi = {10.1109/TCAD.2008.2006088},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenY08,
author = {Song Chen and
Takeshi Yoshimura},
title = {Fixed-Outline Floorplanning: Block-Position Enumeration and a New
Method for Calculating Area Costs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {858--871},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917968},
doi = {10.1109/TCAD.2008.917968},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenYCHL08,
author = {Tung{-}Chieh Chen and
Ping{-}Hung Yuh and
Yao{-}Wen Chang and
Few{-}Juh Huang and
T.{-}Y. Liu},
title = {MP-Trees: {A} Packing-Based Macro Placement Algorithm for Modern Mixed-Size
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1621--1634},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927760},
doi = {10.1109/TCAD.2008.927760},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenYCHL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengCW08,
author = {Lei Cheng and
Deming Chen and
Martin D. F. Wong},
title = {{DDBDD:} Delay-Driven {BDD} Synthesis for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1203--1213},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923088},
doi = {10.1109/TCAD.2008.923088},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengCW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoP08,
author = {Minsik Cho and
David Z. Pan},
title = {A High-Performance Droplet Routing Algorithm for Digital Microfluidic
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1714--1724},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003282},
doi = {10.1109/TCAD.2008.2003282},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoXPP08,
author = {Minsik Cho and
Hua Xiang and
Ruchir Puri and
David Z. Pan},
title = {Track Routing and Optimization for Yield},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {872--882},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917589},
doi = {10.1109/TCAD.2008.917589},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoXPP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiM08,
author = {Munkang Choi and
Linda S. Milor},
title = {Diagnosis of Optical Lithography Faults With Product Test Sets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1657--1669},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927672},
doi = {10.1109/TCAD.2008.927672},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChoiM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouOM08,
author = {Chen{-}Ling Chou and
{\"{U}}mit Y. Ogras and
Radu Marculescu},
title = {Energy- and Performance-Aware Incremental Mapping for Networks on
Chip With Multiple Voltage Levels},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1866--1879},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003301},
doi = {10.1109/TCAD.2008.2003301},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChouOM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuW08,
author = {Chris C. N. Chu and
Yiu{-}Chung Wong},
title = {{FLUTE:} Fast Lookup Table Based Rectilinear Steiner Minimal Tree
Algorithm for {VLSI} Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {70--83},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907068},
doi = {10.1109/TCAD.2007.907068},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuangLLL08,
author = {Wei{-}Shun Chuang and
Shiu{-}Ting Lin and
Wei{-}Chih Liu and
James Chien{-}Mo Li},
title = {Diagnosis of Multiple Scan Chain Timing Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1104--1116},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923258},
doi = {10.1109/TCAD.2008.923258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuangLLL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungLKKK08,
author = {Chaeho Chung and
Soobum Lee and
Byung Man Kwak and
Gawon Kim and
Joungho Kim},
title = {A Delay Line Circuit Design for Crosstalk Minimization Using Genetic
Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {578--583},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915540},
doi = {10.1109/TCAD.2008.915540},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungLKKK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CimattiRT08,
author = {Alessandro Cimatti and
Marco Roveri and
Stefano Tonetta},
title = {Symbolic Compilation of {PSL}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1737--1750},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003303},
doi = {10.1109/TCAD.2008.2003303},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CimattiRT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CinelB08,
author = {Sertac Cinel and
C{\"{u}}neyt F. Bazlama{\c{c}}ci},
title = {A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal
Tree Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2083--2087},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006085},
doi = {10.1109/TCAD.2008.2006085},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CinelB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CollinsC08,
author = {Rebecca L. Collins and
Luca P. Carloni},
title = {Topology-Based Performance Analysis and Optimization of Latency-Insensitive
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2277--2290},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2008914},
doi = {10.1109/TCAD.2008.2008914},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CollinsC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongLR08,
author = {Jason Cong and
Guojie Luo and
Eric Radke},
title = {Highly Efficient Gradient Computation for Density-Constrained Analytical
Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2133--2144},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006158},
doi = {10.1109/TCAD.2008.2006158},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongLR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongX08,
author = {Jason Cong and
Min Xie},
title = {A Robust Mixed-Size Legalization and Detailed Placement Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1349--1362},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925792},
doi = {10.1109/TCAD.2008.925792},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongX08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CuiCT08,
author = {Aijiao Cui and
Chip{-}Hong Chang and
Sofi{\`{e}}ne Tahar},
title = {{IP} Watermarking Using Incremental Technology Mapping at Logic Synthesis
Level},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1565--1570},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927732},
doi = {10.1109/TCAD.2008.927732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CuiCT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CzajkowskiB08,
author = {Tomasz S. Czajkowski and
Stephen Dean Brown},
title = {Functionally Linear Decomposition and Synthesis of Logic Circuits
for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2236--2249},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006144},
doi = {10.1109/TCAD.2008.2006144},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CzajkowskiB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CzyszMRT08,
author = {Dariusz Czysz and
Grzegorz Mrugalski and
Janusz Rajski and
Jerzy Tyszer},
title = {Low-Power Test Data Application in {EDT} Environment Through Decompressor
Freeze},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1278--1290},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923111},
doi = {10.1109/TCAD.2008.923111},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CzyszMRT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DSilvaKW08,
author = {Vijay Victor D'Silva and
Daniel Kroening and
Georg Weissenbacher},
title = {A Survey of Automated Techniques for Formal Software Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1165--1178},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923410},
doi = {10.1109/TCAD.2008.923410},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DSilvaKW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DabiriNMPS08,
author = {Foad Dabiri and
Ani Nahapetian and
Tammara Massey and
Miodrag Potkonjak and
Majid Sarrafzadeh},
title = {General Methodology for Soft-Error-Aware Power Optimization Using
Gate Sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1788--1797},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003268},
doi = {10.1109/TCAD.2008.2003268},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DabiriNMPS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DongR08,
author = {Ning Dong and
Jaijeet S. Roychowdhury},
title = {General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial
Representations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {249--264},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907272},
doi = {10.1109/TCAD.2007.907272},
timestamp = {Fri, 01 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DongR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerEFGHST08,
author = {Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel and
Daniel Tille},
title = {On Acceleration of SAT-Based {ATPG} for Industrial Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1329--1333},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923107},
doi = {10.1109/TCAD.2008.923107},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerEFGHST08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuttVS08,
author = {Shantanu Dutt and
Vinay Verma and
Vishal Suthar},
title = {Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High
Diagnostic Coverage With Application to Online Testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {309--326},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.906992},
doi = {10.1109/TCAD.2007.906992},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuttVS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EngelkePRKSB08,
author = {Piet Engelke and
Ilia Polian and
Michel Renovell and
Sandip Kundu and
Bharath Seshadri and
Bernd Becker},
title = {On Detection of Resistive Bridging Defects by Low-Temperature and
Low-Voltage Testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {327--338},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913382},
doi = {10.1109/TCAD.2007.913382},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/EngelkePRKSB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeySBD08,
author = {G{\"{o}}rschwin Fey and
Stefan Staber and
Roderick Bloem and
Rolf Drechsler},
title = {Automatic Fault Localization for Property Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1138--1149},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923234},
doi = {10.1109/TCAD.2008.923234},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FeySBD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FujiwaraIYO08,
author = {Hideo Fujiwara and
Hiroyuki Iwata and
Tomokazu Yoneda and
Chia Yee Ooi},
title = {A Nonscan Design-for-Testability Method for Register-Transfer-Level
Circuits to Guarantee Linear-Depth Time Expansion Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1535--1544},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927757},
doi = {10.1109/TCAD.2008.927757},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FujiwaraIYO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FungBC08,
author = {Ryan Fung and
Vaughn Betz and
William Chow},
title = {Slack Allocation and Routing to Improve {FPGA} Timing While Repairing
Short-Path Violations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {686--697},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917585},
doi = {10.1109/TCAD.2008.917585},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FungBC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrosseKD08,
author = {Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
title = {Analyzing Functional Coverage in Bounded Model Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1305--1314},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925790},
doi = {10.1109/TCAD.2008.925790},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrosseKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoL08,
author = {J.{-}C. Guo and
Y.{-}M. Lin},
title = {A Compact {RF} {CMOS} Modeling for Accurate High-Frequency Noise Simulation
in Sub-100-nm MOSFETs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1684--1688},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927736},
doi = {10.1109/TCAD.2008.927736},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuoL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HaghdadA08,
author = {Kian Haghdad and
Mohab Anis},
title = {Design-Specific Optimization Considering Supply and Threshold Voltage
Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1891--1901},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003288},
doi = {10.1109/TCAD.2008.2003288},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HaghdadA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HallschmidS08,
author = {Peter Hallschmid and
Resve A. Saleh},
title = {Fast Design Space Exploration Using Local Regression Modeling With
Application to ASIPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {508--515},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915532},
doi = {10.1109/TCAD.2008.915532},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HallschmidS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanP08,
author = {Jeong{-}Ho Han and
In{-}Cheol Park},
title = {{FIR} Filter Synthesis Considering Multiple Adder Graphs for a Coefficient},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {958--962},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917581},
doi = {10.1109/TCAD.2008.917581},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HanP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HassanAE08,
author = {Hassan Hassan and
Mohab Anis and
Mohamed I. Elmasry},
title = {Input Vector Reordering for Leakage Power Reduction in FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1555--1564},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927673},
doi = {10.1109/TCAD.2008.927673},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HassanAE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeldringRTP08,
author = {Alexander Heldring and
Juan Manuel Rius and
Jos{\'{e}} Maria Tamayo and
Josep Parr{\'{o}}n},
title = {Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {265--271},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907236},
doi = {10.1109/TCAD.2007.907236},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeldringRTP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeloueN08,
author = {Khaled R. Heloue and
Farid N. Najm},
title = {Early Analysis and Budgeting of Margins and Corners Using Two-Sided
Analytical Yield Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1826--1839},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003291},
doi = {10.1109/TCAD.2008.2003291},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeloueN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuS08,
author = {Bo Hu and
C.{-}J. Richard Shi},
title = {Simulation of Closely Related Dynamic Nonlinear Systems With Application
to Process-Voltage-Temperature Corner Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {883--892},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917593},
doi = {10.1109/TCAD.2008.917593},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuSMH08,
author = {Yu Hu and
Victor Shih and
Rupak Majumdar and
Lei He},
title = {Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic
Synthesis of FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1751--1760},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003272},
doi = {10.1109/TCAD.2008.2003272},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuSMH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IonutiuRA08,
author = {Roxana Ionutiu and
Joost Rommes and
Athanasios C. Antoulas},
title = {Passivity-Preserving Model Reduction Using Dominant Spectral-Zero
Interpolation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2250--2263},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006160},
doi = {10.1109/TCAD.2008.2006160},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IonutiuRA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IsseninBDD08,
author = {Ilya Issenin and
Erik Brockmeyer and
Bart Durinck and
Nikil D. Dutt},
title = {Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and
Hierarchical Bus-Based Communication Architecture for Multiprocessor
Streaming Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1439--1452},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925781},
doi = {10.1109/TCAD.2008.925781},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IsseninBDD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JabirPM08,
author = {Abusaleh M. Jabir and
Dhiraj K. Pradhan and
Jimson Mathew},
title = {GfXpress: {A} Technique for Synthesis and Optimization of GF(2\({}^{\mbox{m}}\))
Polynomials},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {698--711},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917586},
doi = {10.1109/TCAD.2008.917586},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JabirPM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JaffariA08,
author = {Javid Jaffari and
Mohab Anis},
title = {Variability-Aware Bulk-MOS Device Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {205--216},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907234},
doi = {10.1109/TCAD.2007.907234},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JaffariA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JaffariA08a,
author = {Javid Jaffari and
Mohab Anis},
title = {Statistical Thermal Profile Considering Process Variations: Analysis
and Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1027--1040},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923251},
doi = {10.1109/TCAD.2008.923251},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JaffariA08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JainKSC08,
author = {Himanshu Jain and
Daniel Kroening and
Natasha Sharygina and
Edmund M. Clarke},
title = {Word-Level Predicate-Abstraction and Refinement Techniques for Verifying
{RTL} Verilog},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {366--379},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907270},
doi = {10.1109/TCAD.2007.907270},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JainKSC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JamaaMABILM08,
author = {M. Haykel Ben Jamaa and
Kirsten E. Moselund and
David Atienza and
Didier Bouvet and
Adrian M. Ionescu and
Yusuf Leblebici and
Giovanni De Micheli},
title = {Variability-Aware Design of Multilevel Logic Decoders for Nanoscale
Crossbar Memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2053--2067},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006076},
doi = {10.1109/TCAD.2008.2006076},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JamaaMABILM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JeongN08,
author = {Cheoljoo Jeong and
Steven M. Nowick},
title = {Technology Mapping and Cell Merger for Asynchronous Threshold Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {659--672},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.911339},
doi = {10.1109/TCAD.2007.911339},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JeongN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangC08,
author = {Zhe{-}Wei Jiang and
Yao{-}Wen Chang},
title = {An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion
Algorithm for Antenna Fixing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1055--1065},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923246},
doi = {10.1109/TCAD.2008.923246},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JooCPPCCC08,
author = {Yongsoo Joo and
Yongseok Choi and
Jaehyun Park and
Chanik Park and
Sung Woo Chung and
Eui{-}Young Chung and
Naehyuck Chang},
title = {Energy and Performance Optimization of Demand Paging With OneNAND
Flash},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1969--1982},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006081},
doi = {10.1109/TCAD.2008.2006081},
timestamp = {Mon, 19 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JooCPPCCC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngMS08,
author = {Andrew B. Kahng and
Sudhakar Muddu and
Puneet Sharma},
title = {Defocus-Aware Leakage Estimation and Control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {230--240},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913387},
doi = {10.1109/TCAD.2007.913387},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngMS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngPX08,
author = {Andrew B. Kahng and
Chul{-}Hong Park and
Xu Xu},
title = {Fast Dual-Graph-Based Hotspot Filtering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1635--1642},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927765},
doi = {10.1109/TCAD.2008.927765},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngPX08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngS08,
author = {Andrew B. Kahng and
Kambiz Samadi},
title = {{CMP} Fill Synthesis: {A} Survey of Recent Studies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {3--19},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907061},
doi = {10.1109/TCAD.2007.907061},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngST08,
author = {Andrew B. Kahng and
Puneet Sharma and
Rasit Onur Topaloglu},
title = {Chip Optimization Through STI-Stress-Aware Placement Perturbations
and Fill Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1241--1252},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923083},
doi = {10.1109/TCAD.2008.923083},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngST08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KakadeKP08,
author = {Jayawant Kakade and
Dimitrios Kagaris and
Dhiraj K. Pradhan},
title = {Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional
Scan Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1689--1692},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927763},
doi = {10.1109/TCAD.2008.927763},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KakadeKP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarandikarS08,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Technology Mapping Using Logical Effort for Solving the Load-Distribution
Problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {45--58},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907067},
doi = {10.1109/TCAD.2007.907067},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarandikarS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarfaSMK08,
author = {Chandan Karfa and
Dipankar Sarkar and
Chitta Mandal and
P. Kumar},
title = {An Equivalence-Checking Method for Scheduling Verification in High-Level
Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {556--569},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913390},
doi = {10.1109/TCAD.2007.913390},
timestamp = {Mon, 08 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KarfaSMK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KaushikS08,
author = {Brajesh Kumar Kaushik and
Sankar Sarkar},
title = {Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1150--1154},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923259},
doi = {10.1109/TCAD.2008.923259},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KaushikS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KavousianosKN08,
author = {Xrysovalantis Kavousianos and
Emmanouil Kalligeros and
Dimitris Nikolos},
title = {Test Data Compression Based on Variable-to-Variable Huffman Encoding
With Codeword Reusability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1333--1338},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923100},
doi = {10.1109/TCAD.2008.923100},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KavousianosKN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KettleK08,
author = {Neil Kettle and
Andy King},
title = {An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {764--777},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917592},
doi = {10.1109/TCAD.2008.917592},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KettleK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhandelwalS08,
author = {Vishal Khandelwal and
Ankur Srivastava},
title = {Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon
Tunability Allocation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {610--620},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917960},
doi = {10.1109/TCAD.2008.917960},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KhandelwalS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhursheedIRAH08,
author = {S. Saqib Khursheed and
Urban Ingelsson and
Paul M. Rosinger and
Bashir M. Al{-}Hashimi and
Peter Harrod},
title = {Bridging Fault Test Method With Adaptive Power Management Awareness},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1117--1127},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923247},
doi = {10.1109/TCAD.2008.923247},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KhursheedIRAH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimE08,
author = {Taehoon Kim and
Yungseon Eo},
title = {Analytical {CAD} Models for the Signal Transients and Crosstalk Noise
of Inductance-Effect-Prominent Multicoupled {RLC} Interconnect Lines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1214--1227},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923094},
doi = {10.1109/TCAD.2008.923094},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimHKAK08,
author = {Hyunjin Kim and
Hyejeong Hong and
Hong{-}Sik Kim and
Jin{-}Ho Ahn and
Sungho Kang},
title = {Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor
Using Dynamic Voltage Scaling Efficiency Metric},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2088--2092},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006094},
doi = {10.1109/TCAD.2008.2006094},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KimHKAK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimL08,
author = {Hosung Kim and
John Lillis},
title = {A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2120--2132},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006153},
doi = {10.1109/TCAD.2008.2006153},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KoN08,
author = {Ho Fai Ko and
Nicola Nicolici},
title = {Automated Scan Chain Division for Reducing Shift and Capture Power
During Broadside At-Speed Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2092--2097},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006091},
doi = {10.1109/TCAD.2008.2006091},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KoN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuI08,
author = {Ja Chun Ku and
Yehea I. Ismail},
title = {Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale
Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {241--248},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913393},
doi = {10.1109/TCAD.2007.913393},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KulkarniSB08,
author = {Sarvesh H. Kulkarni and
Dennis Sylvester and
David T. Blaauw},
title = {Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive
Body Bias},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {481--494},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915529},
doi = {10.1109/TCAD.2008.915529},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KulkarniSB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarSPJ08,
author = {Amit Kumar and
Li Shang and
Li{-}Shiuan Peh and
Niraj K. Jha},
title = {System-Level Dynamic Thermal Management for High-Performance Microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {96--108},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907062},
doi = {10.1109/TCAD.2007.907062},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarSPJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LabunJ08,
author = {Andrew Labun and
Karan Jagjitkumar},
title = {Rapid Detailed Temperature Estimation for Highly Coupled {IC} Interconnect},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1840--1851},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003275},
doi = {10.1109/TCAD.2008.2003275},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LabunJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LawGC08,
author = {Chong{-}Fatt Law and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {985--998},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923238},
doi = {10.1109/TCAD.2008.923238},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LawGC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKWC08,
author = {Kuang{-}Yao Lee and
Cheng{-}Kok Koh and
Ting{-}Chi Wang and
Kai{-}Yuan Chao},
title = {Fast and Optimal Redundant Via Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2197--2208},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006151},
doi = {10.1109/TCAD.2008.2006151},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKWC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeePR08,
author = {Hangkyu Lee and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Complete Functional Broadside Tests for Transition Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {583--587},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915531},
doi = {10.1109/TCAD.2008.915531},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeePR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeW08,
author = {Tsung{-}Hsien Lee and
Ting{-}Chi Wang},
title = {Congestion-Constrained Layer Assignment for Via Minimization in Global
Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1643--1656},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927733},
doi = {10.1109/TCAD.2008.927733},
timestamp = {Fri, 08 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiBSZ08,
author = {Yung{-}Ta Li and
Zhaojun Bai and
Yangfeng Su and
Xuan Zeng},
title = {Model Order Reduction of Parameterized Interconnect Networks via a
Two-Directional Arnoldi Process},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1571--1582},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927768},
doi = {10.1109/TCAD.2008.927768},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiBSZ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLCP08,
author = {Xin Li and
Jiayong Le and
Mustafa Celik and
Lawrence T. Pileggi},
title = {Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale
Process and Environmental Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1041--1054},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923241},
doi = {10.1109/TCAD.2008.923241},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLCP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiZP08,
author = {Xin Li and
Yaping Zhan and
Lawrence T. Pileggi},
title = {Quadratic Statistical {MAX} Approximation for Parametric Yield Estimation
of Analog/RF Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {831--843},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917582},
doi = {10.1109/TCAD.2008.917582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiZP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangHT08,
author = {Hsing{-}Chung Liang and
Pao{-}Hsin Huang and
Yan{-}Fei Tang},
title = {Testing Transition Delay Faults in Modified Booth Multipliers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1693--1697},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927761},
doi = {10.1109/TCAD.2008.927761},
timestamp = {Thu, 26 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangHT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinCLCY08,
author = {Chung{-}Wei Lin and
Szu{-}Yu Chen and
Chi{-}Feng Li and
Yao{-}Wen Chang and
Chia{-}Lin Yang},
title = {Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning
Graphs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {643--653},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917583},
doi = {10.1109/TCAD.2008.917583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinCLCY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinHHLC08,
author = {Chung{-}Wei Lin and
Shih{-}Lun Huang and
Kai{-}Chi Hsu and
Meng{-}Xiang Lee and
Yao{-}Wen Chang},
title = {Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction
Based on Spanning Graphs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2007--2016},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006095},
doi = {10.1109/TCAD.2008.2006095},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinHHLC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingZB08,
author = {Andrew C. Ling and
Jianwen Zhu and
Stephen Dean Brown},
title = {Scalable Synthesis and Clustering Techniques Using Decision Diagrams},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {423--435},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915545},
doi = {10.1109/TCAD.2008.915545},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingZB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuHS08,
author = {Yifang Liu and
Jiang Hu and
Weiping Shi},
title = {Buffering Interconnect for Multicore Processor Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2183--2196},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006149},
doi = {10.1109/TCAD.2008.2006149},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuHS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuLLCCKYC08,
author = {Chih{-}Hung Liu and
Hung{-}Yi Liu and
Chung{-}Wei Lin and
Szu{-}Jui Chou and
Yao{-}Wen Chang and
Sy{-}Yen Kuo and
Shih{-}Yi Yuan and
Yu{-}Wei Chen},
title = {An Efficient Graph-Based Algorithm for {ESD} Current Path Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1363--1375},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925779},
doi = {10.1109/TCAD.2008.925779},
timestamp = {Tue, 14 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuLLCCKYC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LongZM08,
author = {Jieyi Long and
Hai Zhou and
Seda Ogrenci Memik},
title = {{EBOARST:} An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner
Tree Construction Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2169--2182},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006098},
doi = {10.1109/TCAD.2008.2006098},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LongZM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuoCWCCW08,
author = {Pei{-}Wen Luo and
Jwu{-}E Chen and
Chin{-}Long Wey and
Liang{-}Chia Cheng and
Ji{-}Jan Chen and
Wen Ching Wu},
title = {Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog
Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2097--2101},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006139},
doi = {10.1109/TCAD.2008.2006139},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuoCWCCW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaL08,
author = {Xiaojun Ma and
Fabrizio Lombardi},
title = {Synthesis of Tile Sets for {DNA} Self-Assembly},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {963--967},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917973},
doi = {10.1109/TCAD.2008.917973},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Macii08,
author = {Enrico Macii},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {1--2},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.911333},
doi = {10.1109/TCAD.2007.911333},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Macii08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaddenP08,
author = {Patrick H. Madden and
David Z. Pan},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {608--609},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.918108},
doi = {10.1109/TCAD.2008.918108},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaddenP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Maffezzoni08,
author = {Paolo Maffezzoni},
title = {Unified Computation of Parameter Sensitivity and Signal-Injection
Sensitivity in Nonlinear Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {781--790},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917596},
doi = {10.1109/TCAD.2008.917596},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Maffezzoni08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MahadevanASBM08,
author = {Shankar Mahadevan and
Federico Angiolini and
Jens Spars{\o} and
Luca Benini and
Jan Madsen},
title = {A Reactive and Cycle-True {IP} Emulator for MPSoC Exploration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {109--122},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.906990},
doi = {10.1109/TCAD.2007.906990},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MahadevanASBM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaheshV08,
author = {R. Mahesh and
A. Prasad Vinod},
title = {A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity
Higher Order Digital Filters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {217--229},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907064},
doi = {10.1109/TCAD.2007.907064},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaheshV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MandalSP08,
author = {Sushanta K. Mandal and
Shamik Sural and
Amit Patra},
title = {{ANN-} and PSO-Based Synthesis of On-Chip Spiral Inductors for {RF}
ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {188--192},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907284},
doi = {10.1109/TCAD.2007.907284},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MandalSP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarculescuG08,
author = {Diana Marculescu and
Siddharth Garg},
title = {Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency
Island Latency-Constrained Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {893--905},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917969},
doi = {10.1109/TCAD.2008.917969},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarculescuG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaslovDMN08,
author = {Dmitri Maslov and
Gerhard W. Dueck and
D. Michael Miller and
Camille Negrevergne},
title = {Quantum Circuit Simplification and Level Compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {436--444},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.911334},
doi = {10.1109/TCAD.2007.911334},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaslovDMN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaslovFM08,
author = {Dmitri Maslov and
Sean M. Falconer and
Michele Mosca},
title = {Quantum Circuit Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {752--763},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917562},
doi = {10.1109/TCAD.2008.917562},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaslovFM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MassierGS08,
author = {Tobias Massier and
Helmut E. Graeb and
Ulf Schlichtmann},
title = {The Sizing Rules Method for {CMOS} and Bipolar Analog Integrated Circuit
Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2209--2222},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006143},
doi = {10.1109/TCAD.2008.2006143},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MassierGS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MehtaMTR08,
author = {Vishal J. Mehta and
Malgorzata Marek{-}Sadowska and
Kun{-}Han Tsai and
Janusz Rajski},
title = {Improving the Resolution of Single-Delay-Fault Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {932--945},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917588},
doi = {10.1109/TCAD.2008.917588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MehtaMTR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MeiR08,
author = {Ting Mei and
Jaijeet S. Roychowdhury},
title = {A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual
Phase Conditions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {59--69},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907259},
doi = {10.1109/TCAD.2007.907259},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MeiR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MemikBM08,
author = {Seda Ogrenci Memik and
Nikolaos Bellas and
Somsubhra Mondal},
title = {Presynthesis Area Estimation of Reconfigurable Streaming Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2027--2038},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006097},
doi = {10.1109/TCAD.2008.2006097},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MemikBM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MemikMNL08,
author = {Seda Ogrenci Memik and
Rajarshi Mukherjee and
Min Ni and
Jieyi Long},
title = {Optimizing Thermal Sensor Allocation for Microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {516--527},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915538},
doi = {10.1109/TCAD.2008.915538},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MemikMNL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MiTCH08,
author = {Ning Mi and
Sheldon X.{-}D. Tan and
Yici Cai and
Xianlong Hong},
title = {Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended
Krylov Subspace Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1996--2006},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006077},
doi = {10.1109/TCAD.2008.2006077},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MiTCH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Miskov-ZivanovM08,
author = {Natasa Miskov{-}Zivanov and
Diana Marculescu},
title = {Modeling and Optimization for Soft-Error Reliability of Sequential
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {803--816},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917591},
doi = {10.1109/TCAD.2008.917591},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Miskov-ZivanovM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Moffitt08,
author = {Michael D. Moffitt},
title = {MaizeRouter: Engineering an Effective Global Router},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2017--2026},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006082},
doi = {10.1109/TCAD.2008.2006082},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Moffitt08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeC08,
author = {Maharaj Mukherjee and
Kanad Chakraborty},
title = {A Randomized Greedy Method for Rectangular-Pattern Fill Problems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1376--1384},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925786},
doi = {10.1109/TCAD.2008.925786},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukhopadhyayMR08,
author = {Saibal Mukhopadhyay and
Hamid Mahmoodi and
Kaushik Roy},
title = {Reduction of Parametric Failures in Sub-100-nm {SRAM} Array Using
Body Bias},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {174--183},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.906995},
doi = {10.1109/TCAD.2007.906995},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MukhopadhyayMR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NeiroukhES08,
author = {Osama Neiroukh and
Stephen A. Edwards and
Xiaoyu Song},
title = {Transforming Cyclic Circuits Into Acyclic Equivalents},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1775--1787},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003305},
doi = {10.1109/TCAD.2008.2003305},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NeiroukhES08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NguyenTWBSK08,
author = {Minh D. Nguyen and
Max Thalmaier and
Markus Wedler and
J{\"{o}}rg Bormann and
Dominik Stoffel and
Wolfgang Kunz},
title = {Unbounded Protocol Compliance Verification Using Interval Property
Checking With Invariants},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2068--2082},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006092},
doi = {10.1109/TCAD.2008.2006092},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NguyenTWBSK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NikolovSD08,
author = {Hristo Nikolov and
Todor P. Stefanov and
Ed F. Deprettere},
title = {Systematic and Automated Multiprocessor System Design, Programming,
and Implementation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {542--555},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.911337},
doi = {10.1109/TCAD.2007.911337},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NikolovSD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OhKCB08,
author = {Sejong Oh and
Tag Gon Kim and
Jeonghun Cho and
Elaheh Bozorgzadeh},
title = {Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {409--422},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915533},
doi = {10.1109/TCAD.2008.915533},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OhKCB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OnaissiN08,
author = {Sari Onaissi and
Farid N. Najm},
title = {A Linear-Time Approach for Static Timing Analysis Covering All Process
Corners},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1291--1304},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923635},
doi = {10.1109/TCAD.2008.923635},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OnaissiN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalWH08,
author = {Muhammet Mustafa Ozdal and
Martin D. F. Wong and
Philip S. Honsinger},
title = {Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed
Boards},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {84--95},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907274},
doi = {10.1109/TCAD.2007.907274},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalWH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PadmanabhanWH08,
author = {Uday Padmanabhan and
Janet Meiling Wang and
Jiang Hu},
title = {Robust Clock Tree Routing in the Presence of Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1385--1397},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925776},
doi = {10.1109/TCAD.2008.925776},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PadmanabhanWH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PakbazniaFP08,
author = {Ehsan Pakbaznia and
Farzan Fallah and
Massoud Pedram},
title = {Charge Recycling in Power-Gated {CMOS} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1798--1811},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003297},
doi = {10.1109/TCAD.2008.2003297},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PakbazniaFP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PalBSD08,
author = {Bhaskar Pal and
Ansuman Banerjee and
Arnab Sinha and
Pallab Dasgupta},
title = {Accelerating Assertion Coverage With Adaptive Testbenches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {967--972},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917975},
doi = {10.1109/TCAD.2008.917975},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PalBSD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PanN08,
author = {David Z. Pan and
Gi{-}Joon Nam},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2105--2106},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2008917},
doi = {10.1109/TCAD.2008.2008917},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PanN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PanditBMP08,
author = {Soumya Pandit and
Sumit K. Bhattacharya and
Chittaranjan A. Mandal and
Amit Patra},
title = {A Fast Exploration Procedure for Analog High-Level Specification Translation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1493--1497},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925785},
doi = {10.1109/TCAD.2008.925785},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PanditBMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PapaLMSLNAM08,
author = {David A. Papa and
Tao Luo and
Michael D. Moffitt and
Chin Ngai Sze and
Zhuo Li and
Gi{-}Joon Nam and
Charles J. Alpert and
Igor L. Markov},
title = {{RUMBLE:} An Incremental Timing-Driven Physical-Synthesis Optimization
Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2156--2168},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006155},
doi = {10.1109/TCAD.2008.2006155},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PapaLMSLNAM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkSDDNPE08,
author = {Sanghyun Park and
Aviral Shrivastava and
Nikil D. Dutt and
Alexandru Nicolau and
Yunheung Paek and
Eugene Earlie},
title = {Register File Power Reduction Using Bypass Sensitive Compiler},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1155--1159},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923254},
doi = {10.1109/TCAD.2008.923254},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkSDDNPE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PatelS08,
author = {Hiren D. Patel and
Sandeep K. Shukla},
title = {On Cosimulating Multiple Abstraction-Level System-Level Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {394--398},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913392},
doi = {10.1109/TCAD.2007.913392},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PatelS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PatilDLWM08,
author = {Nishant Patil and
Jie Deng and
Albert Lin and
H.{-}S. Philip Wong and
Subhasish Mitra},
title = {Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1725--1736},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003278},
doi = {10.1109/TCAD.2008.2003278},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PatilDLWM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PinelloCS08,
author = {Claudio Pinello and
Luca P. Carloni and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Fault-Tolerant Distributed Deployment of Embedded Control Software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {906--919},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917971},
doi = {10.1109/TCAD.2008.917971},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PinelloCS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PlazaMB08,
author = {Stephen Plaza and
Igor L. Markov and
Valeria Bertacco},
title = {Optimizing Nonmonotonic Interconnect Using Functional Simulation and
Logic Restructuring},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2107--2119},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006156},
doi = {10.1109/TCAD.2008.2006156},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PlazaMB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Unspecified Transition Faults: {A} Transition Fault Model for At-Speed
Fault Simulation and Test Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {137--146},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907000},
doi = {10.1109/TCAD.2007.907000},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Primary Input Vectors to Avoid in Random Test Sequences for Synchronous
Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {193--197},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907229},
doi = {10.1109/TCAD.2007.907229},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Scan-Based Delay Test Types and Their Effect on Power Dissipation
During Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {398--403},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907231},
doi = {10.1109/TCAD.2007.907231},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Saturation of n-Detection Test Generation by Different Definitions
With Increased n},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {946--957},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917577},
doi = {10.1109/TCAD.2008.917577},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RajskiTMCMK08,
author = {Janusz Rajski and
Jerzy Tyszer and
Grzegorz Mrugalski and
Wu{-}Tung Cheng and
Nilanjan Mukherjee and
Mark Kassab},
title = {X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {147--159},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907276},
doi = {10.1109/TCAD.2007.907276},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RajskiTMCMK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaudvereSJ08,
author = {Tarvo Raudvere and
Ingo Sander and
Axel Jantsch},
title = {Application and Verification of Local Nonsemantic-Preserving Transformations
in System Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1091--1103},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923249},
doi = {10.1109/TCAD.2008.923249},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaudvereSJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyM08,
author = {Jarrod A. Roy and
Igor L. Markov},
title = {High-Performance Routing at the Nanometer Scale},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1066--1077},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923255},
doi = {10.1109/TCAD.2008.923255},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SamiiSLCP08,
author = {Soheil Samii and
Mikko Selk{\"{a}}l{\"{a}} and
Erik Larsson and
Krishnendu Chakrabarty and
Zebo Peng},
title = {Cycle-Accurate Test Power Modeling and Its Application to SoC Test
Architecture Design and Scheduling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {973--977},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917974},
doi = {10.1109/TCAD.2008.917974},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SamiiSLCP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeomunKS08,
author = {Jun Seomun and
Jae{-}Hyun Kim and
Youngsoo Shin},
title = {Skewed Flip-Flop and Mixed-V\({}_{\mbox{t}}\) Gates for Minimizing
Leakage in Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1956--1968},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006084},
doi = {10.1109/TCAD.2008.2006084},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeomunKS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeongM08,
author = {Seok{-}Won Seong and
Prabhat Mishra},
title = {Bitmask-Based Code Compression for Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {673--685},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917563},
doi = {10.1109/TCAD.2008.917563},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeongM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SesicDM08,
author = {Aleksandra Sesic and
Stanisa Dautovic and
Veljko Malbasa},
title = {Dynamic Power Management of a System With a Two-Priority Request Queue
Using Probabilistic-Model Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {403--407},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.911342},
doi = {10.1109/TCAD.2007.911342},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SesicDM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiXLH08,
author = {Yiyu Shi and
Jinjun Xiong and
Chunchen Liu and
Lei He},
title = {Efficient Decoupling Capacitance Budgeting Considering Operation and
Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1253--1263},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923636},
doi = {10.1109/TCAD.2008.923636},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShiXLH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sinanoglu08,
author = {Ozgur Sinanoglu},
title = {Scan Architecture With Align-Encode},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2303--2316},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2008926},
doi = {10.1109/TCAD.2008.2008926},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Sinanoglu08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinanogluP08,
author = {Ozgur Sinanoglu and
Tsvetomir Petrov},
title = {Isolation Techniques for Soft Cores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1453--1466},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925794},
doi = {10.1109/TCAD.2008.925794},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SinanogluP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghLS08,
author = {Jaskirat Singh and
Zhi{-}Quan Luo and
Sachin S. Sapatnekar},
title = {A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating
Spatial Correlation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {295--308},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.913391},
doi = {10.1109/TCAD.2007.913391},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghLS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghS08,
author = {Jaskirat Singh and
Sachin S. Sapatnekar},
title = {A Scalable Statistical Static Timing Analyzer Incorporating Correlated
Non-Gaussian and Gaussian Parameter Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {160--173},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907241},
doi = {10.1109/TCAD.2007.907241},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SingheeFMR08,
author = {Amith Singhee and
Claire Fang Fang and
James D. Ma and
Rob A. Rutenbar},
title = {Probabilistic Interval-Valued Computation: Toward a Practical Surrogate
for Statistics Inside {CAD} Tools},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2317--2330},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006142},
doi = {10.1109/TCAD.2008.2006142},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SingheeFMR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SongT08,
author = {Chunrong Song and
Spyros Tragoudas},
title = {Identification of Critical Executable Paths at the Architectural Level},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2291--2302},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2008912},
doi = {10.1109/TCAD.2008.2008912},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SongT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SouMD08,
author = {Kin Cheong Sou and
Alexandre Megretski and
Luca Daniel},
title = {A Quasi-Convex Optimization Approach to Parameterized Model Order
Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {456--469},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915544},
doi = {10.1109/TCAD.2008.915544},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SouMD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SpindlerSJ08,
author = {Peter Spindler and
Ulf Schlichtmann and
Frank M. Johannes},
title = {Kraftwerk2 - {A} Fast Force-Directed Quadratic Placement Approach
Using an Accurate Net Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1398--1411},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925783},
doi = {10.1109/TCAD.2008.925783},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SpindlerSJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrivastavaCSSB08,
author = {Ashish Srivastava and
Kaviraj Chopra and
Saumil Shah and
Dennis Sylvester and
David T. Blaauw},
title = {A Novel Approach to Perform Gate-Level Yield Analysis and Optimization
Considering Correlated Variations in Power and Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {272--285},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907227},
doi = {10.1109/TCAD.2007.907227},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SrivastavaCSSB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrivastavaR08,
author = {Shweta Srivastava and
Jaijeet S. Roychowdhury},
title = {Independent and Interdependent Latch Setup/Hold Time Characterization
via Newton-Raphson Solution and Euler Curve Tracking of State-Transition
Equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {817--830},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917595},
doi = {10.1109/TCAD.2008.917595},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SrivastavaR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StratigopoulosM08,
author = {Haralampos{-}G. D. Stratigopoulos and
Yiorgos Makris},
title = {Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {339--351},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907232},
doi = {10.1109/TCAD.2007.907232},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StratigopoulosM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunLMW08,
author = {Jin Sun and
Jun Li and
Dongsheng Ma and
Janet Meiling Wang},
title = {Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under
Limited Descriptions of Uncertainty},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1852--1865},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003300},
doi = {10.1109/TCAD.2008.2003300},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SunLMW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TamHHJZ08,
author = {King Ho Tam and
Yu Hu and
Lei He and
Tom Tong Jing and
Xinyi Zhang},
title = {Dual-V\({}_{\mbox{dd}}\) Buffer Insertion for Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1498--1502},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925784},
doi = {10.1109/TCAD.2008.925784},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TamHHJZ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TennakoonS08,
author = {Hiran Tennakoon and
Carl Sechen},
title = {Nonconvex Gate Delay Modeling and Delay Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1583--1594},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927758},
doi = {10.1109/TCAD.2008.927758},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TennakoonS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TulunayB08,
author = {G{\"{u}}lin Tulunay and
Sina Balkir},
title = {A Synthesis Tool for {CMOS} {RF} Low-Noise Amplifiers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {977--982},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917579},
doi = {10.1109/TCAD.2008.917579},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TulunayB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VankamamidiOL08,
author = {Vamsi Vankamamidi and
Marco Ottavi and
Fabrizio Lombardi},
title = {Two-Dimensional Schemes for Clocking/Timing of {QCA} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {34--44},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907020},
doi = {10.1109/TCAD.2007.907020},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VankamamidiOL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VermaBI08,
author = {Ajay Kumar Verma and
Philip Brisk and
Paolo Ienne},
title = {Data-Flow Transformations to Maximize the Use of Carry-Save Representation
in Arithmetic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1761--1774},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003280},
doi = {10.1109/TCAD.2008.2003280},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VermaBI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VytyazLHMM08,
author = {Igor Vytyaz and
David C. Lee and
Pavan Kumar Hanumolu and
Un{-}Ku Moon and
Kartikeya Mayaram},
title = {Sensitivity Analysis for Oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1521--1534},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927731},
doi = {10.1109/TCAD.2008.927731},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VytyazLHMM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WagnerBA08,
author = {Ilya Wagner and
Valeria Bertacco and
Todd M. Austin},
title = {Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {380--393},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907239},
doi = {10.1109/TCAD.2007.907239},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WagnerBA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WalterLMSY08,
author = {David Walter and
Scott Little and
Chris J. Myers and
Nicholas Seegmiller and
Tomohiro Yoneda},
title = {Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2223--2235},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006159},
doi = {10.1109/TCAD.2008.2006159},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WalterLMSY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangC08,
author = {Zhanglei Wang and
Krishnendu Chakrabarty},
title = {Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering
of Test Patterns},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {352--365},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907228},
doi = {10.1109/TCAD.2007.907228},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHZ08,
author = {Shuai Wang and
Jie S. Hu and
Sotirios G. Ziavras},
title = {Self-Adaptive Data Caches for Soft-Error Reliability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1503--1507},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925789},
doi = {10.1109/TCAD.2008.925789},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHZ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangW08,
author = {Seongmoon Wang and
Wenlong Wei},
title = {An Efficient Unknown BlockingScheme for Low Control Data Volume and
High Observability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {2039--2052},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006093},
doi = {10.1109/TCAD.2008.2006093},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeiD08,
author = {Ying Wei and
Alex Doboli},
title = {Structural Macromodeling of Analog Circuits Through Model Decoupling
and Transformation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {712--725},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917575},
doi = {10.1109/TCAD.2008.917575},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeiD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WolfJM08,
author = {Wayne H. Wolf and
Ahmed Amine Jerraya and
Grant Martin},
title = {Multiprocessor System-on-Chip (MPSoC) Technology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1701--1713},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923415},
doi = {10.1109/TCAD.2008.923415},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WolfJM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Wong08,
author = {Ngai Wong},
title = {Efficient Positive-Real Balanced Truncation of Symmetric Systems Via
Cross-Riccati Equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {470--480},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915534},
doi = {10.1109/TCAD.2008.915534},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Wong08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuH08,
author = {Weixin Wu and
Michael S. Hsiao},
title = {Mining Global Constraints With Domain Knowledge for Improving Bounded
Sequential Equivalence Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {197--201},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907240},
doi = {10.1109/TCAD.2007.907240},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XianLL08,
author = {Changjiu Xian and
Yung{-}Hsiang Lu and
Zhiyuan Li},
title = {Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain
Execution Time},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1467--1478},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925778},
doi = {10.1109/TCAD.2008.925778},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XianLL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangCPW08,
author = {Hua Xiang and
Kai{-}Yuan Chao and
Ruchir Puri and
Martin D. F. Wong},
title = {Is Your Layout-Density Verification Exact? - {A} Fast Exact Deep Submicrometer
Density Calculation Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {621--632},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917962},
doi = {10.1109/TCAD.2008.917962},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiangCPW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangDPCW08,
author = {Hua Xiang and
Liang Deng and
Ruchir Puri and
Kai{-}Yuan Chao and
Martin D. F. Wong},
title = {Fast Dummy-Fill Density Analysis With Coupling Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {633--642},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917963},
doi = {10.1109/TCAD.2008.917963},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiangDPCW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangZCF08,
author = {Dong Xiang and
Yang Zhao and
Krishnendu Chakrabarty and
Hideo Fujiwara},
title = {A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals
for Deterministic {BIST}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {999--1012},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923260},
doi = {10.1109/TCAD.2008.923260},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XiangZCF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieD08,
author = {Lin Xie and
Azadeh Davoodi},
title = {Robust Estimation of Timing Yield With Partial Statistical Information
on Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2264--2276},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006146},
doi = {10.1109/TCAD.2008.2006146},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuC08,
author = {Tao Xu and
Krishnendu Chakrabarty},
title = {A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based
Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1905--1917},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006086},
doi = {10.1109/TCAD.2008.2006086},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XuC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuGFM08,
author = {Chenggang Xu and
Ranjit Gharpurey and
Terri S. Fiez and
Kartikeya Mayaram},
title = {Extraction of Parasitics in Inhomogeneous Substrates With a New Green
Function-Based Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1595--1606},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927766},
doi = {10.1109/TCAD.2008.927766},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuGFM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuL08,
author = {Xiaoxi Xu and
Cheng{-}Chew Lim},
title = {Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1315--1328},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923092},
doi = {10.1109/TCAD.2008.923092},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YaldizDT08,
author = {Soner Yaldiz and
Alper Demir and
Serdar Tasiran},
title = {Stochastic Modeling and Optimization for Energy Management in Multicore
Systems: {A} Video Decoding Case Study},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1264--1277},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923077},
doi = {10.1109/TCAD.2008.923077},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YaldizDT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangHZH08,
author = {Fu{-}Ching Yang and
Wen{-}Kai Huang and
Jing{-}Kun Zhong and
Ing{-}Jer Huang},
title = {Automatic Verification of External Interrupt Behaviors for Microprocessor
Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1670--1683},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927737},
doi = {10.1109/TCAD.2008.927737},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangHZH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangK08,
author = {Yao{-}Joe Joseph Yang and
Chi{-}Wei Kuo},
title = {Generating Scalable and Modular Macromodels for Microchannels Using
the Galerkin-Based Technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {9},
pages = {1545--1554},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927764},
doi = {10.1109/TCAD.2008.927764},
timestamp = {Wed, 24 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangX08,
author = {Jing{-}Ling Yang and
Qiang Xu},
title = {State-Sensitive X-Filling Scheme for Scan Capture Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1338--1343},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923418},
doi = {10.1109/TCAD.2008.923418},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangX08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangZBP08,
author = {Baolin Yang and
Yu Zhu and
Ali Bouaricha and
Joel R. Phillips},
title = {Applications of the Multi-Interval Chebyshev Collocation Method in
{RF} Circuit Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {495--507},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915546},
doi = {10.1109/TCAD.2008.915546},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangZBP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiLSS08,
author = {Yang Yi and
Peng Li and
Vivek Sarin and
Weiping Shi},
title = {A Preconditioned Hierarchical Algorithm for Impedance Extraction of
Three-Dimensional Structures With Multiple Dielectrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1918--1927},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006089},
doi = {10.1109/TCAD.2008.2006089},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiLSS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuDFL08,
author = {Guo Yu and
Wei Dong and
Zhuo Feng and
Peng Li},
title = {Statistical Static Timing Analysis Considering Process Variation Model
Uncertainty},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1880--1890},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2003302},
doi = {10.1109/TCAD.2008.2003302},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuDFL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuWYW08,
author = {Wenjian Yu and
Xiren Wang and
Zuochang Ye and
Zeyi Wang},
title = {Efficient Extraction of Frequency-Dependent Substrate Parasitics Using
Direct Boundary Element Method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1508--1513},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925787},
doi = {10.1109/TCAD.2008.925787},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuWYW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanQVS08,
author = {Lin Yuan and
Gang Qu and
Tiziano Villa and
Alberto L. Sangiovanni{-}Vincentelli},
title = {An {FSM} Reengineering Approach to Sequential Circuit Synthesis by
State Splitting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1159--1164},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923245},
doi = {10.1109/TCAD.2008.923245},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YuanQVS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuhYC08,
author = {Ping{-}Hung Yuh and
Chia{-}Lin Yang and
Yao{-}Wen Chang},
title = {BioRoute: {A} Network-Flow-Based Routing Algorithm for the Synthesis
of Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {11},
pages = {1928--1941},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006140},
doi = {10.1109/TCAD.2008.2006140},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuhYC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZaksYSICGGA08,
author = {Aleksandr Zaks and
Zijiang Yang and
Ilya Shlyakhter and
Franjo Ivancic and
Srihari Cadambi and
Malay K. Ganai and
Aarti Gupta and
Pranav Ashar},
title = {Bitwidth Reduction via Symbolic Interval Analysis for Software Model
Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1513--1517},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925777},
doi = {10.1109/TCAD.2008.925777},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZaksYSICGGA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangJBS08,
author = {Lihong Zhang and
Nuttorn Jangkrajarng and
Sambuddha Bhattacharya and
C.{-}J. Richard Shi},
title = {Parasitic-Aware Optimization and Retargeting of Analog Layouts: {A}
Symbolic-Template Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {791--802},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917594},
doi = {10.1109/TCAD.2008.917594},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangJBS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhengAX08,
author = {Hao Zheng and
Jared Ahrens and
Tian Xia},
title = {A Compositional Method With Failure-Preserving Abstraction for Asynchronous
Design Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1343--1347},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923104},
doi = {10.1109/TCAD.2008.923104},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhengAX08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuGSDJ08,
author = {Changyun Zhu and
Zhenyu (Peter) Gu and
Li Shang and
Robert P. Dick and
Russ Joseph},
title = {Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1479--1492},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925793},
doi = {10.1109/TCAD.2008.925793},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuGSDJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuoHZC08,
author = {Cheng Zhuo and
Jiang Hu and
Min Zhao and
Kangsheng Chen},
title = {Power Grid Analysis and Optimization Using Algebraic Multigrid},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {4},
pages = {738--751},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917587},
doi = {10.1109/TCAD.2008.917587},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuoHZC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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